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BLE121LR Datasheet(PDF) 20 Page - List of Unclassifed Manufacturers |
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BLE121LR Datasheet(HTML) 20 Page - List of Unclassifed Manufacturers |
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20 / 29 page ![]() Bluegiga Technologies Oy Page 20 of 29 6 Design Guidelines 6.1 General Design Guidelines BLE121LR can be used directly with a coin cell battery. Due to relatively high internal resistance of a coin cell battery it is recommended to place a 100uF capacitor in parallel with the battery. The internal resistance of a coin cell battery is initially in the range of 10 ohms but the resistance increases rapidly as the capacity is used. Basically the higher the value of the capacitor the higher is the effective capacity of the battery and thus the longer the life time for the application. The minimum value for the capacitor depends on the end application and the maximum transmit power used. The leakage current of a 100uF capacitor is in the range of 0.5 uA to 3 uA and generally ceramic capacitors have lower leakage current than tantalum or aluminum electrolytic capacitors. Optionally TI’s TPS62730 can be used to reduce the current consumption during TX/RX and data processing stages. TPS62730 is an ultra-low power DC/DC converter with by-pass mode and will reduce the current consumption during transmission nominally by ~20% when using 3V coin cell battery. Figure 16: Example schematic for BLE121LR with a coin cell battery, TPS62730 DCDC converter and an I2C accelerometer 6.2 Layout Guide Lines Use good layout practices to avoid excessive noise coupling to supply voltage traces or sensitive analog signal traces. If using overlapping ground planes use stitching vias separated by max 3 mm to avoid emission from the edges of the PCB. Connect all the GND pins directly to a solid GND plane and make sure that there is a low impedance path for the return current following the signal and supply traces all the way from start to the end. A good practice is to dedicate one of the inner layers to a solid GND plane and one of the inner layers to supply voltage planes and traces and route all the signals on top and bottom layers of the PCB. This |
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