ACPL-P302 datasheet(11/14 Pages) AVAGO

11 / 14 page

Applications Information

Eliminating Negative IGBT Gate Drive

To keep the IGBT firmly off, the ACPL-P302/W302 has a

very low maximum VOL specification of 1.0 V. Minimizing

Rg and the lead inductance from the ACPL-P302/W302

to the IGBT gate and emitter (possibly by mounting the

ACPL-P302/W302 on a small PC board directly above the

IGBT) can eliminate the need for negative IGBT gate drive

in many applications as shown in Figure 17. Care should

be taken with such a PC board design to avoid routing the

IGBT collector or emitter traces close to the ACPL-P302/

W302 input as this can result in unwanted coupling of

transient signals into the input of ACPL-P302/W302 and

degrade performance. (If the IGBT drain must be routed

near the ACPL-P302/W302 input, then the LED should be

reverse biased when in the off state, to prevent the tran-

sient signals coupled from the IGBT drain from turning on

the ACPL-P302/W302.

Selecting the Gate Resistor (Rg)

Step 1: Calculate Rg minimum from the IOL peak specifi-

cation. The IGBT and Rg in Figure 17 can be analyzed as

a simple RC circuit with a voltage supplied by the ACPL-

P302/W302.

Figure 18. Energy Dissipated in the ACPL-P302/W302 and for Each IGBT

Switching Cycle.

Figure 17. Recommended LED Drive and Application Circuit for ACPL-P302/W302

270

CC = 24V

0.1

μF

+5 V

CONTROL

INPUT

74XXX

OPEN

COLLECTOR

+ HVDC

-HVDC

3-PHASE

ACPL-P302/W302

where KICC · Qg · f is the increase in ICC due to switching

and KICC is a constant of 0.001 mA/(nC*kHz). For the circuit

in Figure 17 with IF (worst case) = 10 mA, Rg = 57.5

:, Max

Duty Cycle = 80%, Qg = 100 nC, f = 20 kHz and TAMAX =

85°C:

57.5

0.4

− 1

OLPEAK

−

) f

)(R

) f

;

DutyCycle

ICC

CCBIAS

O(SWITCHING)

O(BIAS)

= (I

= P

= I

= P

The VOL value of 1 V in the previous equation is the VOL at

the peak current of 0.4A. (See Figure 4).

Step 2: Check the ACPL-P302/W302 power dissipation and

increase Rg if necessary. The ACPL-P302/W302 total power

dissipation (PT) is equal to the sum of the emitter power

(PE) and the output power (PO).

@85

°C)

0.3

μJ 20 kHz = 126 mW £ 250 mW ( P

O(MAX)

= (3 mA + (0.001 mA/nC kHz) 20 kHz 100 nC) 24V +

= 10 mA 1.8V 0.8 = 14 mW

The value of 3 mA for ICC in the previous equation is the

max. ICC over entire operating temperature range.

Since PO for this case is less than PO(MAX), Rg = 57.5

: is

alright for the power dissipation.

Rg – GATE RESISTANCE –

100

1.5

4.0

1.0

3.5

Qg = 50 nC

Qg = 100 nC

Qg = 200 nC

Qg = 400 nC

3.0

2.0

0.5

2.5

ACPL-P302 Datasheet(PDF) 11 Page - AVAGO TECHNOLOGIES LIMITED

ACPL-P302 Datasheet(HTML) 11 Page - AVAGO TECHNOLOGIES LIMITED

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Datasheet Download

Link URL