AD7302

–12–

REV. 0

MICROPROCESSOR INTERFACING

AD7302–ADSP-2101/ADSP-2103 Interface

Figure 29 shows an interface between the AD7302 and the

ADSP-2101/ADSP-2103. The fast interface timing associated

with the AD7302 allows easy interface to the ADSP-2101/

ADSP-2103.

ADDR

DECODE

DATA BUS

ADDRESS BUS

CS

DB0

DB7

AD7302*

A/B

DMA0

DMA14

WR

EN

DMD0

DMD15

ADSP-2101*/

ADSP-2103*

WR

DMS

A**

A+1**

**A DECODED ADDRESS FOR DAC A.

LDAC

Figure 29. AD7302–ADSP-2101/ADSP-2103 Interface

Two addresses are decoded to select loading data to either

DAC A or DAC B.

LDAC is permanently tied low in this

circuit, so the selected DAC output is updated on the rising

edge of the

WR signal.

Data is loaded to the AD7302 input register using the following

ADSP-21xx instruction:

DM (DAC) = MR0

MR0 = ADSP-21xx MR0 Register.

DAC = Decoded DAC Address.

AD7302–TMS32020 Interface

Figure 30 shows an interface between the AD7302 and the

TMS32020. The address decoder is used to decode the

addresses for DAC A and DAC B. Data is loaded to the

AD7302 using the following instruction:

OUT DAC, D

DAC = Decoded DAC Address.

D = Data Memory Address.

ADDR

DECODE

DATA BUS

ADDRESS BUS

CS

DB0

DB7

AD7302*

A/B

A0

A15

STRB

EN

DMD0

DMD15

TMS32020

WR

IS

A**

A+1**

**A DECODED ADDRESS FOR DAC A.

LDAC

R/

W

Figure 30. AD7302–TMS32020 Interface

In the circuit shown the

LDAC is hardwired low, thus the

selected DAC output is updated on the rising edge of

WR.

Some applications may require simultaneous updating of both

DACs in the AD7302. In this case the

LDAC signal can be

driven from an external timer or can be controlled by the

microprocessor. One option for simultaneous updating is to

decode the

LDAC from the address bus so that a write opera-

tion at this address will simultaneously update both DAC

outputs. A simple OR gate with one input driven from the

decoded address and the second input from the

WR signal will

implement this function.

AD7302–8051/8088 Interface

Figure 31 shows a serial interface between the AD7302 and the

8051/8088 processors. The address decoder is used to decode

the addresses for DAC A and DAC B.

ADDR

DECODE

ADDRESS/DATA BUS

ADDRESS BUS

DB0

DB7

AD7302*

/B

A8

A15

AD0

AD7

8051/8088

OR

A**

A+1**

**A DECODED ADDRESS FOR DAC A.

ALE

OCTAL

LATCH

Figure 31. AD7302–8051//8088 Interface