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LP3991 Datasheet(PDF) 2 Page - Texas Instruments |
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LP3991 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 20 page ![]() Bottom View Top View Top Marking W B1 A1 B2 A2 VIN VOUT VEN GND B1 A1 B2 A2 VIN VOUT VEN GND LP3991 SNVS296G – DECEMBER 2006 – REVISED JANUARY 2011 www.ti.com Pin Functions Pin Descriptions Packages Pin No. Symbol Name and Function B1 VOUT Voltage output. A Low ESR Ceramic Capacitor should be connected from this pin to GND. (See Application Information) Connect this output to the load circuit. A1 GND Common Ground. Connect to Pad. A2 VEN Enable Input; Enables the Regulator when ≥ 0.95V. Disables the Regulator when ≤ 0.4V. Enable Input has an internal 1.2M Ω pull-down resistor to GND. B2 VIN Voltage Supply Input. A 1.0µF capacitor should be connected from this pin to GND. Connection Diagram Figure 1. 4 Bump Thin Micro SMD, Large Bump These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Links: LP3991 |
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