TPS75005

SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT

VSET = L

VSET = H

VSET = H

VSET = L

3.333 V

3.234

1.818 V

1.919 V

1.764 V

1.862 V

(101%)

(98%)

(101%)

(101%)

(98%)

(98%)

1.206 V

Adjustable,

Adjustable,

Adjustable,

Adjustable,

TPS75005ADJ

greater than 1.24 V

greater than 1.24 V

97% of VOUT1

97% of VOUT2

(1)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

(2)

VOUT1 and VSVS1 are selectable by VSET pin logic with the TPS75005.

ABSOLUTE MAXIMUM RATINGS

(1)

VALUE

UNIT

MIN

MAX

IN, OUT1, OUT2, VMON, VSET, SEQ, OUT1_S, OUT2_S

–0.3

+7.0

V

CT1 CT2, SS1, SS2

–0.3

+3.6

V

EN, VDET, PG, TEST

–0.3

(3)

V

Output current

Temperature

–55

+150

°C

Human body model (HBM) QSS 009-105 (JESD22-A114A)

2

kV

Electrostatic

Charge device model (CDM) QSS 009-147 (JESD22-C101B.01)

500

V

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-

maximum-rated conditions for extended periods my affect device reliability.

(2)

All voltages are with respect to network ground terminal.

(3)

(4)

See Electrical Characteristics.

(5)

ESD testing is performed according to the respective JESD22 JEDEC standard.

2

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Product Folder Link(s): TPS75005