TPS75005

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SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012

The PCB layout of Figure 26 shows that the input and output capacitors C2, C3, and C8 are located near the

respective pins and interconnected with a wide, low-inductance, ground plane that includes the device ground

and the thermal pad ground of the device.

NOTE

The input capacitor ground is routed under the device package through NC, pin-20.

Figure 26. TPS75005EVM-023 Recommended Layout

The PCB typically consists of four layers, minimum. The top (surface) layer and one internal layer are used for

trace/signal routing. One internal layer as well as the bottom layer are devoted to be ground planes that also

function as spreading planes for dissipating heat away from the TPS75005 device. It is very important for proper

function of the device and long-term reliability to conduct heat away from the device. The PowerPAD is soldered

to a ground pad on the PCB that conducts heat away from the device through nine plated vias to the spreading

planes beneath. The internal spreading layer in this case consists of four square inches of 1-ounce copper, and

the bottom layer consists of an equal area of 2-ounce copper. Additional spreading layers should be added, if

necessary, to a given application.

Copyright © 2011–2012, Texas Instruments Incorporated

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Product Folder Link(s): TPS75005