TSB41AB1PHP datasheet(44/71 Pages) TI1

44 / 71 page

TSB41AB1

IEEE 1394a2000 ONEPORT CABLE

TRANSCEIVER/ARBITER

SLLS423I − JUNE 2000 − REVISED MARCH 2005

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

output differentiation

The TSB41AB1 implements differentiation circuitry functionally equivalent to that shown in Figure 20 on the

bidirectional CTL0 , CTL1, and D0 – D7 terminals. The TSB41AB1 also implements an input hysteresis buffer

on the LREQ input to convert this signal to the correct logic level when differentiated. The LLC must also

implement similar output differentiation and input hysteresis circuitry on its CTL and D terminals and output

differentiation circuitry on its LREQ terminal.

3-State Output

Driver

Input Buffer With

Hysteresis

DIN

DOUT

ISO

OUTEN

INIT

SYSCLK

To/From

Internal

Device Logic

D Terminal

Figure 20. Input/Output Differentiation Logic

LLC service request

To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the LLC sends

a serial bit stream on the LREQ terminal as shown in Figure 21.

LR(n-2)

LR3

LR2

LR1

LR0

LR(n-1)

NOTE: Each cell represents one clock sample time, and n is the number of bits in the request stream.

Figure 21. LREQ Request Stream

The length of the stream varies depending on the type of request as shown in Table 12.

Table 12. Request Stream Bit Length

REQUEST TYPE

NUMBER OF BITS

Bus request

7 or 8

Read register request

Write register request

Acceleration control request

TSB41AB1PHP Datasheet(PDF) 44 Page - Texas Instruments

TSB41AB1PHP Datasheet(HTML) 44 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

Datasheet Download

Link URL