TSB41AB1PHP datasheet(14/71 Pages) TI1

14 / 71 page

TSB41AB1

IEEE 1394a2000 ONEPORT CABLE

TRANSCEIVER/ARBITER

SLLS423I − JUNE 2000 − REVISED MARCH 2005

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued)

TERMINAL

NAME

NUMBER

TYPE

I/O

DESCRIPTION

NAME

PAP

PHP

GQE/ZQE

TYPE

I/O

DESCRIPTION

RESET

CMOS

Logic reset input. Asserting this terminal low resets the internal logic. An internal

pullup resistor to VDD is provided so only an external delay capacitor is required for

proper power-up operation (see power-up reset in the Application Information

section). The RESET terminal also incorporates an internal pulldown which is

activated when the PD input is asserted high. This input is otherwise a standard logic

input, and may also be driven by an open-drain type driver.

CMOS

Test control input. This input is used in manufacturing test of the TSB41AB1. For

normal use this terminal may be tied to GND through a 1-k

Ω pulldown resistor or it

may be tied to GND directly.

CMOS

Test control input. This input is used in manufacturing test of the TSB41AB1. For

normal use this terminal should be tied to GND.

SYSCLK

CMOS

System clock output. Provides a 49.152-MHz clock signal, synchronized with data

transfers, to the LLC.

TESTM

CMOS

Test control input. This input is used in manufacturing test of the TSB41AB1. For

normal, use this terminal should be tied to VDD through a 1-kΩ resistor.

TPA+

Cable

I/O

Twisted-pair cable A differential signal terminals. Board traces from the pair of

positive and negative differential signal terminals should be kept matched and as

TPA−

Cable

I/O

positive and negative differential signal terminals should be kept matched and as

short as possible to the external load resistors and to the cable connector.

TPB+

Cable

I/O

Twisted-pair cable B differential signal terminals. Board traces from the pair of

positive and negative differential signal terminals should be kept matched and as

TPB−

Cable

I/O

positive and negative differential signal terminals should be kept matched and as

short as possible to the external load resistors and to the cable connector.

TPBIAS

Cable

I/O

Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for

proper operation of the twisted-pair cable drivers and receivers, and for signaling to

the remote nodes that there is an active cable connection.

Crystal

−

Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant

fundamental mode crystal. The optimum values for the external shunt capacitors are

dependent on the specifications of the crystal used (see crystal selection in the

Application Information section). When an external clock source is used, XI should

be the input and XO should be left open, and the clock must be supplied before the

device is taken out of reset.

NOTE: It is strongly recommended that signals tied to VDD use a 1-kΩ resistor (minimum). Tying signals directly to VCC may result in ESD failures.

Signals tied to ground may be tied directly.

TSB41AB1PHP Datasheet(PDF) 14 Page - Texas Instruments

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