MF10-N

SNOS547C – JUNE 1999 – REVISED APRIL 2013

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PIN DESCRIPTIONS

LP(1,20), BP(2,19), N/AP/HP(3,18) The second order lowpass, bandpass and notch/allpass/highpass outputs.

These outputs can typically sink 1.5 mA and source 3 mA. Each output typically swings to within 1V of

each supply.

INV(4,17) The inverting input of the summing op-amp of each filter. These are high impedance inputs, but the

impedance, current inputs).

S1(5,16) S1 is a signal input pin used in the allpass filter configurations (see modes 4 and 5). The pin should be

driven with a source impedance of less than 1 k

Ω. If S1 is not driven with a signal it should be tied to

AGND (mid-supply).

configuring the filter in its various modes of operation.

D

D

been brought out separately so they can be bypassed by separate capacitors, if desired. They can be

externally tied together and bypassed by a single capacitor.

D

A

D

LSh(9) Level shift pin; it accommodates various clock levels with dual or single supply operation. With dual ±5V

supplies, the MF10-N can be driven with CMOS clock levels (±5V) and the LSh pin should be tied to the

system ground. If the same supplies as above are used but only TTL clock levels, derived from 0V to +5V

supply, are available, the LSh pin should be tied to the system ground. For single supply operation (0V

D

+5V and the LSh pin should also be tied to the system ground for TTL clock levels. LSh should be biased

at +5V for CMOS clock levels in 10V single-supply applications.

CLKA(10), CLKB(11) Clock inputs for each switched capacitor filter building block. They should both be of the

same level (TTL or CMOS). The level shift (LSh) pin description discusses how to accommodate their

levels. The duty cycle of the clock should be close to 50% especially when clock frequencies above 200

kHz are used. This allows the maximum time for the internal op-amps to settle, which yields optimum filter

operation.

50/100/CL(12) By tying this pin high a 50:1 clock-to-filter-center-frequency ratio is obtained. Tying this pin at mid-

supplies (i.e. analog ground with dual supplies) allows the filter to operate at a 100:1 clock-to-center-

frequency ratio. When the pin is tied low (i.e., negative supply with dual supplies), a simple current limiting

circuit is triggered to limit the overall supply current down to about 2.5 mA. The filtering action is then

aborted.

AGND(15) This is the analog ground pin. This pin should be connected to the system ground for dual supply

operation or biased to mid-supply for single supply operation. For a further discussion of mid-supply

biasing techniques see the Applications Information. For optimum filter performance a “clean” ground must

be provided.

Definition of Terms

the MF10-N, and is the frequency of maximum bandpass gain (Figure 17).

can be observed as the frequency of a notch at the allpass output (Figure 26).

divided by the

−3 dB bandwidth of the 2nd order bandpass filter (Figure 17). The value of Q determines the

shape of the 2nd order filter responses as shown in Figure 22.

8

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