TLV2544, TLV2548

2.7V TO 5.5V, 12BIT, 200KSPS, 4/8CHANNEL, LOW POWER

SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN

SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003

20

POST OFFICE BOX 655303

−0.3 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−55

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0

°C to 70°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV2544/48I

−40

°C to 85°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

260

°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

DERATING FACTOR

‡

TA = 70°C

TA = 85°C

TA = 125°C

PACKAGE

TA ≤ 25 C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C‡

TA = 70 C

POWER RATING

TA = 85 C

POWER RATING

TA = 125 C

POWER RATING

D

1110 mW

8.9 mW/

°C

710 mW

577 mW

222 mW

DW

1294 mW

10.4 mW/

°C

828 mW

673 mW

259 mW

16 PW

839 mW

6.7 mW/

°C

537 mW

437 mW

—

20 PW

977 mW

7.8 mW/

°C

625 mW

508 mW

—

‡ This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA). Thermal resistance is not production tested and the values

given are for informational purposes only.

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, VCC

2.7

3.3

5.5

V

Analog input voltage (see Note 4)

0

VCC

V

High level control input voltage, VIH

2.1

V

Low-level control input voltage, VIL

0.6

V

Delay time, delay from CS falling edge to FS rising edge, td(CSL-FSH)

(See Figure 16)

0.5

SCLKs

Delay time, delay time from 16th SCLK falling edge to CS rising edge (FS = 1), or

17th rising edge (FS is active) td(SCLK-CSH) (See Figures 16, and 19)

0.5

SCLKs

Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKL

(See Figure 16)

20

ns

Hold time, FS hold high after SCLK falling edge, th(FSH-SCLKL) (See Figure 16)

30

ns

Pulse width, CS high time, twH(CS) (See Figures 16 and 19)

100

ns

Pulse width, FS high time, twH(FS) (See Figure 16)

0.75

1

SCLKs

SCLK cycle time, tc(SCLK)

VCC = 2.7 V to 3.6 V

75

10000

ns

SCLK cycle time, tc(SCLK)

(See Figures 16, and 19)

VCC = 4.5 V to 5.5V

50

10000

ns

NOTE 4: When binary output format is used, analog input voltages greater than that applied to REFP convert as all ones (111111111111), while

input voltages less than that applied to REFM convert as all zeros (000000000000). The device is functional with reference down to

1 V. (VREFP − VREFM − 1); however, the electrical specifications are no longer applicable.