ADS820 datasheet(9/21 Pages) TI1

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ADS820

SBAS037B

THEORY OF OPERATION

The ADS820 is a high-speed, sampling A/D converter with

pipelining. It uses a fully differential architecture and digital

error correction to ensure 10-bit resolution. The differential

track-and-hold circuit is shown in Figure 1. The switches are

controlled by an internal clock that has a non-overlapping,

two-phase signal,

φ1 and φ2. At the sampling time the input

signal is sampled on the bottom plates of the input capaci-

tors. In the next clock phase,

φ2, the bottom plates of the

input capacitors are connected together and the feedback

capacitors are switched to the op amp output. At this time,

the charge redistributes between CI and CH, completing one

track-and-hold cycle. The differential output is a held DC

representation of the analog input at the sample time. The

track-and-hold circuit can also convert a single-ended input

signal into a fully differential signal for the quantizer.

The pipelined quantizer architecture has nine stages with

each stage containing a 2-bit quantizer and a 2-bit Digital-to-

Analog Converter (DAC), as shown in Figure 2. Each 2-bit

quantizer stage converts on the edge of the sub-clock, which

is twice the frequency of the externally applied clock. The

output of each quantizer is fed into its own delay line to

FIGURE 1. Input Track-and-Hold Configuration with Timing

Signals.

FIGURE 2. Pipeline A/D Converter Architecture.

φ1

φ2

φ1

φ2

φ1

φ2

φ1

φ2

OUT

Op Amp

Bias

Op Amp

Bias

Input Clock (50%)

Internal Non-overlapping Clock

–

B1 (MSB)

B10 (LSB)

2-Bit

DAC

2-Bit

Flash

Input

T&H

Digital Delay

2-Bit

DAC

2-Bit

Flash

Digital Delay

2-Bit

Flash

Digital Delay

2-Bit

DAC

2-Bit

Flash

Digital Delay

STAGE 1

STAGE 2

STAGE 8

STAGE 9

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