Electronic Components Datasheet Search
  English  ▼

X  

ADC08100 Datasheet(PDF) 2 Page - Texas Instruments

Click here to check the latest version.
Part # ADC08100
Description  ADC08100 8-Bit, 20 Msps to 100 Msps, 1.3 mW/Msps A/D Converter
PDF  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC08100 Datasheet(HTML) 2 Page - Texas Instruments

  ADC08100 Datasheet HTML 1Page - Texas Instruments ADC08100 Datasheet HTML 2Page - Texas Instruments ADC08100 Datasheet HTML 3Page - Texas Instruments ADC08100 Datasheet HTML 4Page - Texas Instruments ADC08100 Datasheet HTML 5Page - Texas Instruments ADC08100 Datasheet HTML 6Page - Texas Instruments ADC08100 Datasheet HTML 7Page - Texas Instruments ADC08100 Datasheet HTML 8Page - Texas Instruments ADC08100 Datasheet HTML 9Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 2 / 28 page
background image
VD
DGND
VRT
VRM
256
1
SWITCHES
CLOCK
GEN
COARSE/FINE
COMPARATORS
ENCODER
& ERROR
CORRECTION
17
CLK
17
COARSE/FINE
COMPARATORS
ENCODER
& ERROR
CORRECTION
17
VA
(pin 18)
AGND
VIN
8
8
OUTPUT
DRIVERS
MUX
8
8
DATA
OUT
PD
DR VD
DR GND
(pin 17)
VRB
VIN GND
ADC08100
SNAS060I – JUNE 2000 – REVISED MAY 2013
www.ti.com
Block Diagram
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin No.
Symbol
Equivalent Circuit
Description
6
VIN
Analog signal input. Conversion range is VRB to VRT.
Analog Input that is the high (top) side of the reference ladder
of the ADC. Nominal range is 1.0V to VA. Voltage on VRT and
3
VRT
VRB inputs define the VIN conversion range. Bypass well. See
THE ANALOG INPUT for more information.
Mid-point of the reference ladder. This pin should be bypassed
9
VRM
to a clean, quiet point in the analog ground plane with a 0.1
µF capacitor.
Analog Input that is the low side (bottom) of the reference
ladder of the ADC. Nominal range is 0.0V to (VRT – 1.0V).
10
VRB
Voltage on VRT and VRB inputs define the VIN conversion
range. Bypass well. See THE ANALOG INPUT for more
information.
Power Down input. When this pin is high, the converter is in
23
PD
the Power Down mode and the data output pins hold the last
conversion result.
CMOS/TTL compatible digital clock Input. VIN is sampled on
24
CLK
the falling edge of CLK input.
2
Submit Documentation Feedback
Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: ADC08100



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com