AS3635 datasheet(12/21 Pages) TAOS

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AS3635

Datasheet - D e t a i l e d D e s c r i p t i o n

A typical charging cycle and its voltages and current on the different pins and signals are shown in Figure 18:

Figure 18. AS3635 Charging Cycle Details

The input CHARGE is set to high and charging begins (1).

During a single cycle, the internal NMOS transistor connects the pin SW to PGND (2). Therefore the current ISW rises

(3) until it reaches ISW current limit (4). Then the energy is transferred to the secondary side of the transformer and the

voltage VCFLASH on the flash capacitor CFLASH rises (5).

The output voltage VCFLASH gradually increases and once it hits the end of charge detection threshold (6) (detected on

VSW during the off time of the NMOS transistor between SW and PGND) 8 times (7)

, DONE is pulled low (8). When

CHARGE is set to low afterwards (9), DONE returns to high (10) finishing a full charging cycle.

Note:

For simplicity the number of actual charging cycles (NMOS SW on/off) are reduced in Figure 18.

1. The 8 cycles required for actual detection of the end of charge conditions are not shown in Figure 18.

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AS3635 Datasheet(PDF) 12 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS