74HC_HCT573

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2012. All rights reserved.

Product data sheet

Rev. 5 — 15 August 2012

4 of 21

NXP Semiconductors

74HC573; 74HCT573

Octal D-type transparent latch; 3-state

5.

Pinning information

5.1 Pinning

5.2 Pin description

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as

supply pin or input

Fig 5.

Pin configuration DIP20, SO20, SSOP20 and

TSSOP20

Fig 6.

Pin configuration DHVQFN20

001aae076

1

2

3

4

5

6

7

8

9

10

12

11

14

13

16

15

18

17

20

19

OE

D0

Q0

D1

Q1

D2

Q2

D3

Q3

D4

Q4

D5

Q5

D6

Q6

D7

Q7

GND

LE

74HC573

74HCT573

001aae077

74HC573

74HCT573

Transparent top view

Q7

D6

D7

Q6

D5

Q5

D4

Q4

D3

Q3

D2

Q2

D1

Q1

D0

Q0

9

12

8

13

7

14

6

15

5

16

4

17

3

18

2

19

terminal 1

index area

Table 2.

Pin description

Symbol

Pin

Description

OE

1

3-state output enable input (active LOW)

D[0:7]

2, 3, 4, 5, 6, 7, 8, 9

data input

GND

10

ground (0 V)

LE

11

latch enable input (active HIGH)

Q[0:7]

19, 18, 17, 16, 15, 14, 13, 12 3-state latch output

20

supply voltage