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WM1811A Datasheet(PDF) 233 Page - Wolfson Microelectronics plc |
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WM1811A Datasheet(HTML) 233 Page - Wolfson Microelectronics plc |
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233 / 328 page  Production Data WM1811A w PD, November 2013, Rev 4.1 233 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2 AIF2_ADCDAT_S RC 0 ADCDAT2 Source select 0 = AIF2 ADCDAT2 1 = GPIO8/DACDAT3 For selection 1, the GPIO8 pin must also be configured as DACDAT3. 1 AIF2_DACDAT_S RC 0 AIF2 DACDAT Source select 0 = DACDAT2 1 = GPIO8/DACDAT3 For selection 1, the GPIO8 pin must also be configured as DACDAT3. 0 AIF1_DACDAT_S RC 0 AIF1 DACDAT Source select 0 = DACDAT1 1 = GPIO8/DACDAT3 Note that, for selection 1, the GPIO8 pin must be configured as DACDAT3. Register 06h Power Management (6) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R21 (15h) Input Mixer (1) 8 IN1RP_MIXINR_ BOOST 0 IN1RP Pin (PGA Bypass) to MIXINR Gain Boost. This bit selects the maximum gain setting of the IN1RP_MIXINR_VOL register. 0 = Maximum gain is +6dB 1 = Maximum gain is +15dB 7 IN1LP_MIXINL_B OOST 0 IN1LP Pin (PGA Bypass) to MIXINL Gain Boost. This bit selects the maximum gain setting of the IN1LP_MIXINL_VOL register. 0 = Maximum gain is +6dB 1 = Maximum gain is +15dB 6 INPUTS_CLAMP 0 Input pad VMID clamp 0 = Clamp de-activated 1 = Clamp activated Register 15h Input Mixer (1) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R24 (18h) Left Line Input 1&2 Volume 8 IN1_VU 0 Input PGA Volume Update Writing a 1 to this bit will cause IN1L and IN1R input PGA volumes to be updated simultaneously 7 IN1L_MUTE 1 IN1L PGA Mute 0 = Disable Mute 1 = Enable Mute 6 IN1L_ZC 0 IN1L PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only 4:0 IN1L_VOL [4:0] 0_1011 IN1L Volume -16.5dB to +30dB in 1.5dB steps Register 18h Left Line Input 1&2 Volume |
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