HD74AC112/HD74ACT112

Dual JK Negative Edge-Triggered Flip-Flop

Description

The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to

each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level

of the J and K inputs may change when the clock is High and the bistable will perform according to the

Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs

on the falling edge of the clock pulse.

Features

• Outputs Source/Sink 24 mA

• HD74ACT112 has TTL-Compatible Inputs

Pin Arrangement

1

2

3

4

5

6

7

8

GND

16

15

14

13

12

11

10

9

(Top view)