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HD74ACT112 Datasheet(PDF) 2 Page - Hitachi Semiconductor |
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HD74ACT112 Datasheet(HTML) 2 Page - Hitachi Semiconductor |
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2 / 10 page ![]() HD74AC112/HD74ACT112 2 Logic Symbol 3 J1 Q1 Q1 K1 CP1 CD1 J2 Q2 Q2 K2 CP2 CD2 SD1 SD2 5 410 11 13 12 6 9 7 1 2 15 14 VCC = Pin16 GND = Pin8 Pin Names J 1, J2, K1, K2 Data Inputs CP 1, CP2 Clock Pulse Inputs (Active Falling Edge) C D1, CD2 Direct Clear Inputs (Active Low) S D1, SD2 Direct Set Inputs (Active Low) Q 1, Q2, Q1, Q 2 Outputs Asynchronous Inputs: Low input to S D sets Q to High level Low input to C D sets Q to Low level Clear and Set are independent of clock Simultaneous Low on C D and SD makes both Q and Q High |
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