Supertex inc.

Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888

www.supertex.com

TP0610T

General Description

This low threshold enhancement-mode (normally-off) transistor

utilizes a vertical DMOS structure and Supertex’s well-proven

silicon-gate manufacturing process. This combination produces a

device with the power handling capabilities of bipolar transistors

and with the high input impedance and positive temperature

coefficient inherent in MOS devices. Characteristic of all MOS

structures, this device is free from thermal runaway and thermally-

induced secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a wide range

of switching and amplifying applications where very low threshold

voltage, high breakdown voltage, high input impedance, low input

capacitance, and fast switching speeds are desired.

P-Channel Enhancement Mode

Vertical DMOS FETs

Product Marking

TO-236AB (SOT-23) (T)

T50W

W = Code for week sealed

= “Green” Packaging

DRAIN

SOURCE

GATE

Ordering Information

Device

Package Options

BV

(V)

R

DS(ON)

(max)

(Ω)

I

D(ON)

(min)

(mA)

TO-236AB (SOT-23)

TP0610T

TP0610T-G

-60

10

-50

TO-236AB (SOT-23) (T)

Features

Applications

Pin Configuration

Package may or may not include the following marks: Si or

Parameter

Value

Drain-to-source voltage

BV

DSS

Drain-to-gate voltage

BV

DGS

Gate-to-source voltage

±20V

Operating and storage temperature

Absolute Maximum Ratings are those values beyond which damage to the device

may occur. Functional operation under these conditions is not implied. Continuous

operation of the device at the absolute rating level may affect device reliability. All

voltages are referenced to device ground.

Absolute Maximum Ratings

For packaged products, -G indicates package is RoHS compliant (‘Green’).

Consult factory for die / wafer form part numbers.

Refer to Die Specification VF21 for layout and dimensions.