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HT62L256 Datasheet(PDF) 1 Page - Holtek Semiconductor Inc |
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HT62L256 Datasheet(HTML) 1 Page - Holtek Semiconductor Inc |
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1 / 10 page ![]() HT62L256 CMOS 32K´8 Low Power SRAM Block Diagram Pin Assignment Rev. 0.00 1 August 15, 2002 Features · Operation voltage: 2.7V~3.3V · Low power consumption: - Operating current: 20mA max. - Standby current: 2mA · High speed access time: 70ns · Input levels are LVTTL-compatible · Automatic power down when chip is deselected · Three state outputs · Fully static operation · Data retention supply voltage as low as 2.0V · Easy expansion with CS and OE options · 28-pin SOP/TSOP package General Description The HT62L256 is a 262,144-bit static random access memory organized into 32,768 words by 8 bits and oper- ating from a low power range of 2.7V to 3.3V supply volt- age. It is fabricated with high performance CMOS process that provides both high speed and low power feature with typical standby current of 2 mA and maxi- mum access time of 70ns. The HT62L256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The HT62L256 supports the JEDEC standard 28-pin SOP and TSOP package. A d d r e s s B u f f e r s R e a d / W r i t e C o n t r o l L o g i c V D D V S S W E O E C S A 0 A 1 4 X - D e c Y - D e c M e m o r y C e l l A r r a y ( 3 2 K ´ 8 B i t s S e n s e A m p l i f i e r O u t p u t B u f f e r s D 0 D 7 Preliminary O E A 1 1 A 9 A 8 A 1 3 W E V D D A 1 4 A 1 2 A 7 A 6 A 5 A 4 A 3 A 1 0 C S D 7 D 6 D 5 D 4 D 3 V S S D 2 D 1 D 0 A 0 A 1 A 2 1 1 4 1 5 2 8 H T 6 2 L 2 5 6 2 8 S O P - A A 1 4 A 1 2 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 V S S V D D W E A 1 3 A 8 A 9 A 1 1 O E A 1 0 C S D 7 D 6 D 5 D 4 D 3 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 H T 6 2 L 2 5 6 2 8 T S O P - A |
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