HT62L256 datasheet(3/10 Pages) HOLTEK

3 / 10 page

A.C. Characteristics

Ta=25

°C, VDD=3.0V±10%

Symbol

Parameter

Min.

Typ.

Max.

Unit

Read cycle

tRC

Read Cycle Time

¾¾

tAA

Address Access Time

¾¾

tACS

Chip Selection Access Time

¾¾

tAOE

Output Enable to Valid Outputs

¾¾

tCLZ*

Chip Selection to Output in Low-Z

¾¾

tOLZ*

Output Enabled to Output in Low-Z

¾¾

tCHZ*

Chip Deselected to Output in High-Z

¾¾

tOHZ*

Output Disable to Output in High-Z

¾¾

tOH

Output Hold from Address Change

¾¾

Write cycle

tWC

Write Cycle Time

¾¾

tCW

Chip Selection to End of Write

¾¾

tAS

Address Setup Time

¾¾

tAW

Address Valid to End of Write

¾¾

tWP

Write Pulse Width

¾¾

tWR

Write Recovery Time

¾¾

tWHZ

Write to Output in High

-Z

¾¾

tDW

Data Valid to End of Write

¾¾

tDH

Data Hold from End of Write

¾¾

tOW

Output Active from End of Write

¾¾

Note:

1. A write cycle occurs during the overlap of a low CS and a low WE

2. OE may be both high and low in a write cycle

3. tAS is specified from CS or WE, whichever occurs last

4. tWP is an overlap time of a low CS and a low WE

5. tWR,tDW and tDH are specified from CS or WE, whichever occurs first

6. tWHZ is specified by the time when DATA OUT is floating and not defined by the output level

7. When the I/O pins are in data output mode, they should not be forced with inverse signals

HT62L256

Rev. 0.00

August 15, 2002

Preliminary

HT62L256 Datasheet(PDF) 3 Page - Holtek Semiconductor Inc

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