AT90PWM2 datasheet(167/365 Pages) ATMEL

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4317K–AVR–03/2013

AT90PWM2/3/2B/3B

• Bit 7:6 – PPRE01:0 : PSC 0 Prescaler Select

This two bits select the PSC input clock division factor. All generated waveform will be modified

by this factor.

• Bit 5 – PBFM0 : Balance Flank Width Modulation

When this bit is clear, Flank Width Modulation operates on On-Time 1 only.

When this bit is set, Flank Width Modulation operates on On-Time 0 and On-Time 1.

• Bit 4 – PAOC0B : PSC 0 Asynchronous Output Control B

When this bit is set, Fault input selected to block B can act directly to PSCOUT01 output. See

Section “PSC Input Configuration”, page 148.

• Bit 3 – PAOC0A : PSC 0 Asynchronous Output Control A

When this bit is set, Fault input selected to block A can act directly to PSCOUT00 output. See

Section “PSC Input Configuration”, page 148.

• Bit 2 – PARUN0 : PSC 0 Autorun

When this bit is set, the PSC 0 starts with PSC2. That means that PSC 0 starts :

•

when PRUN2 bit in PCTL2 is set,

•

or when PARUN2 bit in PCTL2 is set and PRUN1 bit in PCTL1 register is set.

Thanks to this bit, 2 or 3 PSCs can be synchronized (motor control for example)

• Bit 1 – PCCYC0 : PSC 0 Complete Cycle

When this bit is set, the PSC 0 completes the entire waveform cycle before halt operation

requested by clearing PRUN0. This bit is not relevant in slave mode (PARUN0 = 1).

• Bit 0 – PRUN0 : PSC 0 Run

Writing this bit to one starts the PSC 0.

When set, this bit prevails over PARUN0 bit.

16.25.12 PSC 1 Control Register – PCTL1

Table 16-14. PSC 0 Prescaler Selection

PPRE01

PPRE00

Description PWM2/3

Description PWM2B/3B

No divider on PSC input clock

Divide the PSC input clock by 4

Divide the PSC input clock by 16

Divide the PSC input clock by 32

Divide the PSC clock by 64

Divide the PSC clock by 256

Bit

654

PPRE11

PPRE10

PBFM1

PAOC1B

PAOC1A

PARUN1

PCCYC1

PRUN1

PCTL1

Read/Write

R/W

Initial Value

AT90PWM2 Datasheet(PDF) 167 Page - ATMEL Corporation

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