AT90PWM2 datasheet(47/365 Pages) ATMEL

47 / 365 page

4317K–AVR–03/2013

AT90PWM2/3/2B/3B

Notes:

1. Values are guidelines only..

2. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)

9.0.3

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level

is defined in Table 9-1. The POR is activated whenever V

CC is below the detection level. The

POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply

voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

device is kept in RESET after V

CC rise. The RESET signal is activated again, without any delay,

when V

CC decreases below the detection level.

Figure 9-2.

MCU Start-up, RESET Tied to V

Table 9-1.

Reset Characteristics(1)

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

VPOT

Power-on Reset Threshold

Voltage (rising)

1.4

2.3

Power-on Reset Threshold

Voltage (falling)(2)

1.3

2.3

VRST

RESET Pin Threshold Voltage

0.2Vcc

0.85Vcc

tRST

Minimum pulse width on RESET

400

VPOR

VCC start voltage to ensure

internal Power-on RESET signal

-0.05

GND

+0.05

CCRR

VCC Rise Rate to ensure internal

Power-on RESET signal

0.3

V/ms

RESET

TIME-OUT

INTERNAL

RESET

TOUT

POT

RST

AT90PWM2 Datasheet(PDF) 47 Page - ATMEL Corporation

AT90PWM2 Datasheet(HTML) 47 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL