AT90PWM2 datasheet(174/365 Pages) ATMEL

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4317K–AVR–03/2013

AT90PWM2/3/2B/3B

This feature is useful to detect that a PSC output doesn’t change due to a frozen external input

signal.

• Bit 5 – PSEIn : PSC n Synchro Error Interrupt

This bit is set by hardware when the update (or end of PSC cycle) of the PSCn configured in

auto run (PARUNn = 1) does not occur at the same time than the PSCn-1 which has generated

the input run signal. (For PSC0, PSCn-1 is PSC2).

Must be cleared by software by writing a one to its location.

This feature is useful to detect that a PSC doesn’t run at the same speed or with the same phase

than the PSC master.

• Bit 4 – PEVnB : PSC n External Event B Interrupt

This bit is set by hardware when an external event which can generates a capture or a retrigger

from Retrigger/Fault block B occurs.

Must be cleared by software by writing a one to its location.

This bit can be read even if the corresponding interrupt is not enabled (PEVEnB bit = 0).

• Bit 3 – PEVnA : PSC n External Event A Interrupt

This bit is set by hardware when an external event which can generates a capture or a retrigger

from Retrigger/Fault block A occurs.

Must be cleared by software by writing a one to its location.

This bit can be read even if the corresponding interrupt is not enabled (PEVEnA bit = 0).

• Bit 2:1 – PRNn1:0 : PSC n Ramp Number

Memorization of the ramp number when the last PEVnA or PEVnB occured.

• Bit 0 – PEOPn: End Of PSC n Interrupt

This bit is set by hardware when PSC n achieves its whole cycle.

Must be cleared by software by writing a one to its location.

Table 16-18. PSC n Ramp Number Description

PRNn1

PRNn0

Description

The last event which has generated an interrupt occurred during ramp 1

The last event which has generated an interrupt occurred during ramp 2

The last event which has generated an interrupt occurred during ramp 3

The last event which has generated an interrupt occurred during ramp 4

AT90PWM2 Datasheet(PDF) 174 Page - ATMEL Corporation