AT90PWM2 datasheet(207/365 Pages) ATMEL

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4317K–AVR–03/2013

AT90PWM2/3/2B/3B

This setting is available in EUSART mode only when data bits are level encoded (in Manchester

the parity checker and generator are not available).

• Bit 3 – USBS: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores

this setting.

In EUSART mode, the USBS bit has the same behavior and the EUSB bit of the EUSART allows

to configure the number of stop bit for the receiver in this mode.

• Bit 2:1 – UCSZ1:0: Character Size

The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Char-

acter SiZe) in a frame the Receiver and Transmitter use.

When the EUSART mode is set, these bits have no effect.

• Bit 0 – UCPOL: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is

used. The UCPOL bit sets the relationship between data output change and data input sample,

and the synchronous clock (XCK).

Table 18-5.

UPM Bits Settings

UPM1

UPM0

Parity Mode

Disabled

Reserved

Enabled, Even Parity

Enabled, Odd Parity

Table 18-6.

USBS Bit Settings

USBS

Stop Bit(s)

01-bit

12-bit

Table 18-7.

UCSZ Bits Settings

UCSZ2

UCSZ1

UCSZ0

Character Size

5-bit

6-bit

7-bit

8-bit

100

Reserved

101

Reserved

110

Reserved

9-bit

AT90PWM2 Datasheet(PDF) 207 Page - ATMEL Corporation

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