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AT90PWM2 Datasheet(PDF) 232 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 232 Page - ATMEL Corporation |
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232 / 365 page  232 4317K–AVR–03/2013 AT90PWM2/3/2B/3B AC2IE in AC2CON register is set. Anyway, this bit is cleared by writing a logical one on it. This bit can also be used to synchronize ADC or DAC conversions. • Bit 5– AC1IF: Analog Comparator 1 Interrupt Flag Bit This bit is set by hardware when comparator 1 output event triggers off the interrupt mode defined by AC1IS1 and AC1IS0 bits in AC1CON register. This bit is cleared by hardware when the corresponding interrupt vector is executed in case the AC1IE in AC1CON register is set. Anyway, this bit is cleared by writing a logical one on it. This bit can also be used to synchronize ADC or DAC conversions. • Bit 5– AC0IF: Analog Comparator 0 Interrupt Flag Bit This bit is set by hardware when comparator 0 output event triggers off the interrupt mode defined by AC0IS1 and AC0IS0 bits in AC0CON register. This bit is cleared by hardware when the corresponding interrupt vector is executed in case the AC0IE in AC0CON register is set. Anyway, this bit is cleared by writing a logical one on it. This bit can also be used to synchronize ADC or DAC conversions. • Bit 2– AC2O: Analog Comparator 2 Output Bit AC2O bit is directly the output of the Analog comparator 2. Set when the output of the comparator is high. Cleared when the output comparator is low. • Bit 1– AC1O: Analog Comparator 1 Output Bit AC1O bit is directly the output of the Analog comparator 1. Set when the output of the comparator is high. Cleared when the output comparator is low. • Bit 0– AC0O: Analog Comparator 0 Output Bit AC0O bit is directly the output of the Analog comparator 0. Set when the output of the comparator is high. Cleared when the output comparator is low. 20.2.5 Digital Input Disable Register 0 – DIDR0 • Bit 3:2 – ACMPM and ACMP2D: ACMPM and ACMP2 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding Analog pin is dis- abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to one of these pins and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 20.2.6 Digital Input Disable Register 1– DIDR1 • Bit 5, 2: ACMP0D and ACMP1 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding analog pin is dis- abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an Bit 76543210 ADC7D ADC6D ADC5D ADC4D ADC3D ACMPM ADC2D ACMP2D ADC1D ADC0D DIDR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 00000000 Bit 76543210 - -ACMP0D AMP0PD AMP0ND ADC10D ACMP1D ADC9D AMP1PD ADC8D AMP1ND DIDR1 Read/Write - - R/W R/W R/W R/W R/W R/W Initial Value 00000000 |
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