AT90PWM2 datasheet(294/365 Pages) ATMEL

294 / 365 page

294

4317K–AVR–03/2013

AT90PWM2/3/2B/3B

Figure 25-8. Parallel Programming Timing, Loading Sequence with Timing Requirements

(1)

Note:

1. The timing requirements shown in Figure 25-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to load-

ing operation.

Figure 25-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with

Timing Requirements

(1)

Note:

1. The timing requirements shown in Figure 25-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to read-

ing operation.

Table 25-14. Parallel Programming Characteristics, V

CC = 5V ± 10%

Symbol

Parameter

Min

Typ

Max

Units

VPP

Programming Enable Voltage

11.5

12.5

IPP

Programming Enable Current

250

A

tDVXH

Data and Control Valid before XTAL1 High

tXLXH

XTAL1 Low to XTAL1 High

200

tXHXL

XTAL1 Pulse Width High

150

tXLDX

Data and Control Hold after XTAL1 Low

tXLWL

XTAL1 Low to WR Low

XTAL1

PAGEL

PLXH

XLXH

XLPH

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE)

LOAD DATA

(LOW BYTE)

LOAD DATA

(HIGH BYTE)

LOAD DATA

LOAD ADDRESS

(LOW BYTE)

XTAL1

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE)

READ DATA

(LOW BYTE)

READ DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

BVDV

OLDV

XLOL

OHDZ

AT90PWM2 Datasheet(PDF) 294 Page - ATMEL Corporation

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