HCPL7840 datasheet(6/12 Pages) HP

6 / 12 page

1-253

Figure 1. Input Offset Voltage Test Circuit.

Figure 2. Input Offset Change vs.

Temperature.

Figure 3. Input Offset Change vs.

VDD1 and VDD2.

VDD – SUPPLY VOLTAGE – V

0.2

0.1

4.6

0.3

4.8

5.0

5.2

TA = 25°C

-0.1

vs. VDD1 (VDD2 = 5 V)

4.4

5.6

5.4

vs. VDD2 (VDD1 = 5 V)

TA – TEMPERATURE – °C

-0.2

-0.6

-20

0.6

VDD1 = 5 V

VDD2 = 5 V

-0.8

0.2

0.4

-40

100

-0.4

040

Notes:

1. If VIN- is brought above VDD1 - 2 V

with respect to GND1 an internal test

mode may be activated. This test

mode is not intended for customer

use.

2. Exact offset value is dependent on

layout of external bypass capacitors.

The offset value in the data sheet

corresponds to HP’s recommended

layout (see Figures 25 and 26).

3. Nonlinearity is defined as half of the

peak-to-peak output deviation from

the best-fit gain line, expressed as a

percentage of the full-scale differen-

tial output voltage.

4. Because of the switched capacitor

nature of the sigma-delta A/D

converter, time-averaged values are

shown.

5. CMRRIN is defined as the ratio of the

gain for differential inputs applied

between pins 2 and 3 to the gain for

common mode inputs applied to both

pins 2 and 3 with respect to pin 4.

6. When the differential input signal

exceeds approximately 320 mV, the

outputs will limit at the typical values

shown.

7. Short-circuit current is the amount of

output current generated when either

output is shorted to VDD2 or ground.

HP does not recommend operation

under these conditions.

8. CMR (also known as IMR or Isolation

Mode Rejection) specifies the

minimum rate of rise of a common

mode noise signal applied across the

isolation boundary at which small

output perturbations begin to appear.

These output perturbations can occur

with both the rising and falling edges

of the common mode waveform and

may be of either polarity. A CMR

failure is defined as a perturbation

exceeding 200 mV at the output of

the recommended application circuit

(Figure 23). See applications section

for more information on CMR.

9. CMRR is defined as the ratio of

differential signal gain (signal applied

differentially between pins 2 and 3)

to the common mode gain (input pins

tied to pin 4 and the signal applied

between the input and the output of

the isolation amplifier) at 60 Hz,

expressed in dB.

10. Output noise comes from two primary

sources: chopper noise and sigma-

delta quantization noise. Chopper

noise results from chopper stabiliza-

tion of the output op-amps. It occurs

at a specific frequency (typically 500

kHz) and is not attenuated by the on-

chip output filter. The on-chip filter

does eliminate most, but not all, of

the sigma-delta quantization noise.

An external filter circuit may be

easily added to the external post-

amplifier to reduce the total RMS

output noise. See applications section

for more information.

11. Data sheet value is the amplitude of

the transient at the differential output

of the HCPL-7840 when a 1 VP-P,

1 MHz square wave with 100 ns rise

and fall times (measured at pins 1

and 8) is applied to both VDD1 and

VDD2.

12. In accordance with UL1577, each

isolation amplifer is proof tested by

applying an insulation test voltage

≥ 3000 V

RMS for 1 second (leakage

current detection limit II-O ≤ 5 µA).

13. Device considered a two terminal

device: Pins 1, 2, 3 and 4 connected

together; pins 5, 6, 7 and 8

connected together.

0.1 µF

VDD2

VOUT

HCPL-7840

0.1 µF

10 K

VDD1

+15 V

0.1 µF

-15 V

–

AD624CD

GAIN = 100

0.47

µF

0.47

µF

Figure 4. Output Voltages vs. Input

Voltage.

VIN – INPUT VOLTAGE – V

2.5

2.0

1.5

-0.4

4.0

-0.2

0.2

VDD1 = 5 V

VDD2 = 5 V

TA = 25°C

1.0

3.0

3.5

-0.6

0.6

0.4

POSITIVE

OUTPUT

NEGATIVE

OUTPUT

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