HDMP-1012 datasheet(10/42 Pages) HP

10 / 42 page

582

HDMP-1012 (Tx) Timing

Figure 6 shows the Tx timing

diagram. Under normal

operations, the Tx PLL locks an

internally generated clock to the

incoming STRBIN. The incoming

data, D0-D19, ED, FF, DAV*,

CAV*, and FLAG, are latched by

this internal clock. For

MDFSEL=0, the input rate of

STRBIN is expected to be the

same as the parallel data rate. For

MDFSEL=1, STRBIN should be 1/

2 of the incoming parallel data

rate. The data must be valid

before it’s sampled for the set-up

time (ts), and remain valid after

it’s sampled for the hold time (th).

The set-up and hold times are

referenced to STRBIN. This

reference is the positive edge of

STRBIN for MDFSEL=0, and is 1/

2 the frame period from the

positive or negative edge of

STRBIN for MDFSEL=1.

STRBOUT appears after this

reference with a delay of Tstrb.

The rate of STRBOUT is always

the same as the word rate of the

incoming data, independent of

MDFSEL.

The start of a frame, D0, in the

high speed serial output occurs

after a delay of td after the rising

edge of the STRBIN. The typical

value of td may be calculated by

using the following formula:

td = ( 2 * serial bit duration -

0.5 ns) ns

Figure 6. HDMP-1012 (Tx) Timing Diagram.

HDMP-1012 (Tx) Timing Characteristics

Tc = 0

°C to +85°C, V

EE = -4.5 V to -5.5 V

Symbol

Parameter

Units

Min.

Typ.

Max.

Setup Time, for Rising Edge of STRBIN Relative to

nsec

D0-D19, ED, FF, DAV*, CAV* and FLAG

Hold Time, for Rising Edge of STRBIN Relative to

nsec

D0-D19, ED, FF, DAV*, CAV* and FLAG

∆T

strb

STRBOUT - STRBIN Delay

nsec

1.5

1/2 FRAME PERIOD

tstrb

D-FIELD

C-FIELD

STRBIN

MDFSEL = 0

STRBIN

MDFSEL = 1

D00 - D19

ED, FF

DAV*, CAV*

FLAG

STRBOUT

DOUT

HCLK

HDMP-1012 Datasheet(PDF) 10 Page - Agilent(Hewlett-Packard)

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