HDMP-1012 datasheet(29/42 Pages) HP

29 / 42 page

601

The lock detect circuit samples

STRBIN with phase shifted

versions of STRBOUT. If the

samples are not the proper

values, the LOCKED signal goes

low and stays low for at least two

frames.

Rx Operation Principles

The HDMP-1014 (Rx) is

monolithically implemented in a

high performance 25 GHz ft

bipolar process. When properly

configured, the Rx can accept

20B/24B CIMT line code frames,

and then output parallel 16B/17B/

20B/21B Data Word or 14B/18B

Control Word. The Rx provides

the following functions for link

operation:

• Clock recovery

• Frame synchronization

• Data recovery

• Demultiplexing

• Frame decoding

• Frame error detection

• Link state control

Rx Encoding

Figure 5 shows a simplified block

diagram of the receiver. The data

path consists of an Input Select,

an Input Sampler, a Frame

Demultiplexer, a Control Field (C-

Field) Decoder, and a Data Field

(D-Field) Decoder. An on-chip

phase-locked loop (PLL) is used

to extract timing reference from

the serial input (DIN or LIN). The

PLL includes a Phase-Frequency

Detector, a Loop Filter, and a

variable-frequency oscillator

(VCO). All the RX internal clock

signals are generated from a

Clock Generator. The Clock

Generator can be driven either by

internal VCO or external signal,

TCLK, depending on the Clock

Select configuration.

Integrated on the chip is a Link-

Control State Machine for link

status monitoring and link

startup. Figure 13 shows the

details of the Input Select. The

Input Select chooses either

nominal serial data (DIN) or

loopback (LIN) signal for the

Input Sampler’s input. If loopback

enable (LOOPEN) is asserted, the

LIN input is selected. Also

included in the Input Selector is

cable equalization circuitry. When

coaxial cable is used as the

transmission media, by setting

EQEN=1 (enable equalization),

the equalization circuitry is in the

DIN signal path and can

compensate for high-frequency

cable loss.

Because the Data Field of the

CIMT line code can be either 16-

bit or 20-bit wide, the width

selection for Rx is made by

setting the input pin M20SEL

(Figure 5). If M20SEL=1, then

the Rx is configured to accept

serial input with 20-bit data field,

i.e., 24 bits per frame. If M20SEL

= 0, 16-bit data field is selected.

HDMP-1014 (Rx) Phase-

Locked Loop

A more detailed block diagram for

the Rx phase-locked loop (PLL) is

shown in Figure 14. In the PLL,

the phase of the serial input, SIN,

is compared with synchronizing

signals from the internal clock

generator, using either a phase

detector or a frequency detector.

The frequency detector disable

signal, FDIS, selects which

detector to use. If synchronization

in a link is not yet established, the

HDMP-1012 (Tx) should send out

Fill Frame 0 (FF0) or Fill Frame 1

(FF1) to the remote Rx. By

setting FDIS=0, the Rx uses

Figure 13. HDMP-1014 (Rx) Input Selector.

CABLE EQ

EQEN

SIN

DIN

LIN

LOOPEN

HDMP-1012 Datasheet(PDF) 29 Page - Agilent(Hewlett-Packard)

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