AT32A datasheet(49/336 Pages) ATMEL

49 / 336 page

ATmega32A [DATASHEET]

Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014

13.2

Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 12-2 shows a functional description of

one I/O-port pin, here generically called Pxn.

Figure 13-2. General Digital I/O

(1)

Note:

1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

I/O, SLEEP, and PUD are common

to all ports.

13.2.1

Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register Description” on

page 66, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and

the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured

as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch

the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The

port pins are tri-stated when a reset condition becomes active, even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If

PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an inter-

mediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must

occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the

difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can

be set to disable all pull-ups in all ports.

clk

RPx

RRx

WPx

RDx

WDx

PUD

SYNCHRONIZER

WDx:

WRITE DDRx

WPx:

WRITE PORTx

RRx:

READ PORTx REGISTER

RPx:

READ PORTx PIN

PUD:

PULLUP DISABLE

clk

I/O:

I/O CLOCK

RDx:

READ DDRx

RESET

CLR

PORTxn

CLR

DDxn

PINxn

SLEEP

SLEEP:

SLEEP CONTROL

Pxn

I/O

AT32A Datasheet(PDF) 49 Page - ATMEL Corporation

AT32A Datasheet(HTML) 49 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL