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ICS83052I Datasheet(PDF) 1 Page - Integrated Device Technology |
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ICS83052I Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 17 page ![]() 2:1, Single-Ended Multiplexer ICS83052I DATA SHEET ICS83052I REVISION B DECEMBER 8, 2011 1 ©2011 Integrated Device Technology, Inc. GENERAL DESCRIPTION The ICS83052I is a low skew, 2:1, Single-ended Multiplexer. The ICS83052I has two selectable single-ended clock inputs and one single-ended clock output. The output has a V DDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage trans-lation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug. The device operates up to 250MHz and is packaged in an 8 TSSOP. BLOCK DIAGRAM PIN ASSIGNMENT FEATURES • 2:1 single-ended multiplexer • Q nominal output impedance: 15 Ω (V DDO = 3.3V) • Maximum output frequency: 250MHz • Propagation delay: 2.7ns (maximum), (V DD = VDDO = 3.3V) • Input skew: 160ps (maximum), (V DD = VDDO = 3.3V) • Part-to-part skew: 490ps (maximum), (V DD = VDDO = 3.3V) • Additive phase jitter, RMS at 155.52MHz (12kHz - 20MHz): 0.18ps (typical), (V DD = VDDO = 3.3V) • Operating supply modes: V DD/VDDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V • -40°C to 85°C ambient operating temperature • Available in standard (RoHS 5) and lead-free (RoHS 6) packages CLK0 CLK1 SEL0 OE Q ICS83052I 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View VDDO GND CLK1 VDD 1 2 3 4 Q SEL0 CLK0 OE 8 7 6 5 |
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