GMS81608K datasheet(46/79 Pages) HYNIX

46 / 79 page

STOP MODE

For applications where power consumption is a critical

factor, device provides reduced power of STOP.

An instruction that STOP causes that to be the last

instruction executed before going into the Stop mode.

In the Stop mode, the on-chip oscillator is stopped.

With the clock frozen, all functions are stopped, but

the on-chip RAM and Control registers are held. The

port pins out the values held by their respective port

data register Rx, port direction register RxDD. The

status of peripherals during Stop mode is shown below.

Peripheral

Status

RAM

Retain

Control registers

Retain

I/O

Retain

Oscillation

Stop

XIN

Low

X OUT

High

In the Stop mode of operation, VDD can be reduced to

minimize power consumption. Care must be taken,

however, to ensure that VDD is not reduced before the

Stop mode is invoked, and that VDD is restored to its

normal operating level, before the Stop mode is termi-

nated. The reset should not be activated before VDD is

restored to its normal operating level, and must be held

active long enough to allow the oscillator to restart and

stabilize (minimum 20 msec).

Caution:

The NOP instruction have to be written more than

two to next line of the STOP instruction.

Ex)

STOP

NOP

Release Stop Mode

The exit from Stop mode is hardware reset or external

interrupt. Reset redefines all the Control registers but

does not change the on-chip RAM. External interrupts

allow both on-chip RAM and Control registers to

retain their values.

If I-flag = 1, the normal interrupt response takes place.

If I-flag = 0, the chip will resume execution starting

with the instruction following the STOP instruction. It

will not vector to interrupt service routine.

When exit from Stop mode by external interrupt from

Stop mode, enough oscillation stabilization time is

required to normal operation. Figure 37 shows the

timing diagram. When release the Stop mode, the

EXTERNAL

INTERRUPT

INTERNAL

CLOCK

OSCILLATOR

tST > 20 ms

NORMAL OPERATION

BASIC INTERVAL

TIMER COUNTER

CLEAR BASIC

INTERVAL TIMER

N+2

N+1

STABILIZATION

TIME

NORMAL OPERATION

STOP MODE

STOP INSTRUCTION

EXECUTION

Figure 37. Timing of Stop Release by External Interrupt

GMS81604/08

LG Semicon

GMS81608K Datasheet(PDF) 46 Page - Hynix Semiconductor

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