7

ICS1574B

]

3

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P

Register Mapping — ICS1574B

automatically generate all register values based on requirements. Contact factory for details.

BIT(S)

BIT REF.

DESCRIPTION

1 – 4

PCLK[0]..PCLK[3]

Sets PCLK divider modulus according to this table.

These bits are set to implement a divide-by-four on power-up.

5, 6

Reserved

Must be set to 0.

7

Reserved

Must be set to 1.

8

SELXTAL

Normally set to 0. When set to logic 1, passes the reference

frequency to the post-scaler instead of the PLL output

(defaults to 1 on power-up).

9

Reserved

Must be set to 0.

10

Reserved

Must be set to 1.

11, 12

Reserved

Must be set to 0.

13 – 14

S[0]..S[1]

PLL post-scaler / test mode select bits.