ICS674-01

User Configurable Divider

MDS 674-01 A

5

Revision 033199

Printed 11/15/00

Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 •(408)295-9800tel•(408)295-9818fax

PRELIMINARY INFORMATION

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (stresses be oond these can permanentl damage the deevice)

Supply Voltage, VDD

Referenced to GND

7

V

Inputs

Referenced to GND

-0.5

VDD+0.5

V

Clock Output

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperature

0

70

°C

Ambient Operating Temperature

I version

-40

85

°C

Soldering Temperature

Max of 10 seconds

260

°C

Storage Temperature

-65

150

°C

DC CHARACTERISTICS (VDD = 5.0V unless oth

herwise noted)

Operating Voltage, VDD

3

5.5

V

Input High Voltage, VIH

All A, B, and S pins

2

V

Input Low Voltage, VIL

All A, B, and S pins

0.8

V

Input High Voltage, VIH, INA and INB only

(VDD/2)+1

VDD/2

V

Input Low Voltage, VIL, INA and INB only

VDD/2

(VDD/2)-1

V

Output High Voltage, VOH

IOH=-25mA

2.4

V

Output Low Voltage, VOL

IOL=25mA

0.4

V

IDD, Op. Supply Cur., DivA=DivB=20 at 3.3 V

No Load, fin=100 MHz

3

mA

IDD, Op. Supply Cur., DivA=DivB=20 at 5 V

No Load, fin=100 MHz

5

mA

Short Circuit Current, outputs

±70

mA

On-Chip Pull-up Resistor

A, B, S select pins

270

k

Ω

Input Capacitance

A, B, S select pins

5

pF

AC CHARACTERISTICS (VDD = 5.0V unless oth

herwise noted)

Input Frequency, Divider A

at 3.3 V

0

135

MHz

Input Frequency, Divider B

at 3.3 V

0

180

MHz

Input Frequency, Divider A

at 5 V

0

200

MHz

Input Frequency, Divider B

at 5 V

0

235

MHz

Input Frequency, Divider A (Industrial temperature) at 3.3 V at 85 °C

0

125

MHz

Input Frequency, Divider B (Industrial temperature) at 3.3 V at 85 °C

0

170

MHz

Input Frequency, Divider A (Industrial temperature) at 5 V at 85 °C

0

190

MHz

Input Frequency, Divider B (Industrial temperature) at 5 V at 85 °C

0

220

MHz

Output Clock Rise Time

0.8 to 2.0V

1

ns

Output Clock Fall Time

2.0 to 0.8V

1

ns

OUTB Clock Duty Cycle (see note)

at VDD/2

45

49 to 51

55

%

OUTB Clock Duty Cycle, odd post dividers

at VDD/2, except PD=1

40

60

%

OUTA Clock Duty Cycle (see note)

at VDD/2

20

98.5

%

Note:

The duty cycle of OUTA is dependent on the selected divide. This is because OUTA goes low for 2 input

clock cycles on INA. So, for example, if a divide of 20 is selected, the duty cycle will be 90%.

Similarly, if PD=1 is selected for OUTB, the duty cycle will be dependent on the selected divide. In this

case OUTB goes high for approximately 8 input clock cycles on INB.