ICS674-01

User Configurable Divider

MDS 674-01 A

1

Revision 033199

Printed 11/15/00

Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 •(408)295-9800tel•(408)295-9818fax

PRELIMINARY INFORMATION

• Packaged as 28 pin SSOP (150 mil body)

• Supports ICS673 PLL Building Block

• User determines the divide by setting input pins

• Pull-ups on all select inputs

• Includes one 7-bit Divider for OUTA

• Includes one 9-bit Divider and one selectable

Post Divider for OUTB

• Operating voltages of 3.3 V or 5.0 V

• Industrial temperature range available

• 25mA drive capability at TTL levels

• Advanced, low power CMOS process

The ICS674-01 consists of 2 separate

configurable dividers. The A Divider is a 7 bit

divider and can divide by 3 to 129. The

B Divider consists of a 9 bit divider followed by a

post divider. The 9 bit divider can divide by 12

to 519. The post divider has eight settings of

1, 2, 4, 5, 6, 7, 8 and 10 giving a maximum total

divide of 5190. The A and B Dividers can be

cascaded to give a maximum divide of 669510.

The ICS674-01 supports the ICS673 PLL

Building Block and enables the user to build a full

custom PLL synthesizer.

Block Diagram

Description

Features

Divider A

(7-Bit)

Output

Buffer

Post

Divider

Divider B

(9-Bit)

7

2

3

VDD

GND

INA

INB

OUTA

OUTB

B8:B0

A6:A0

93

S2:S0

Output

Buffer