3

ICS9148-18

Technical Pin Function Descriptions

VDD(1,2)

This is the power supply to the internal core logic of the

device as well as the clock output buffers for REF0, PCICLK

(0:4),andPCICLK_F.

This pin operates at 3.3V volts. Clocks from the buffers that

it supplies will have a voltage swing from Ground to this

level. For the actual guaranteed high and low voltage levels

for the clocks, please consult the DC parameter table in this

data sheet.

VDDL

This is the power supply for the CPUCLK output buffers.

The voltage level for these outputs may be 2.5 or 3.3volts.

Clocks from the buffers that this pin supplies will have a

voltage swing from Ground to VDDL. For the actual

guaranteed high and low voltage levels of these Clocks,

please consult the DC parameter table in this data sheet.

GND(1,2)

This is the power supply ground (common or negative) return

pin for the internal core logic and all the PCI output buffers.

GNDL

This is the ground for CPUCLK output buffers.

X1

This input pin serves one of two functions. When the device

is used with a crystal, X1 acts as the input pin for the

reference signal that comes from the crystal. When the device

is driven by an external clock signal, X1 is the device input

pin for that reference clock. This pin also has an internal

Crystal loading capacitor that is connected to ground. With

a nominal value of 33pF, no external load cap is needed for a

X2

This Output pin is used only when the device uses a crystal

as the reference frequency source. In this mode of operation,

X2 is an output signal that drives (or excites) the crystal. The

X2 pin also has an internal loading capacitor, nominally 33pF.

CPUCLK(0:1)

These output pins are the clock outputs that drive processor

and other CPU related circuitry that requires clocks which

are in tight skew tolerance with the CPU clock. The voltage

swing of these clocks is controlled by the voltage level

applied to the VDDL pin of the device. See the Functionality

Table for a list of the specific frequencies that are available

for these clocks and the selection codes to produce them.

REF0

The REF Output is fixed frequency clock that runs at the

same frequency as the Input Reference Clock or the Crystal

(typically 14.31818MHz) attached across X1 and X2.

PCICLK_F

This Output is equal to PCICLK(0:4) and is FREE RUNNING,

and will not be stopped by PCI_STOP#.

PCICLK(0:4)

These output clocks generate all the PCI timing requirements

for a Pentium/Pro based system. They conform to the

current PCI specification.

SELECT 100/66.6MHz#

This input pin controls the frequency of the clocks at the

CPU & PCICLK output pins. If a logic “1” value is present on

this pin, the 100MHz clock is selected. If a logic “0” is used,

the 66.6MHz frequency is selected. The PCI clock is

multiplexed to run at 33.3MHz for both select cases. PCI is

synchronous at the rising edge of PCI to the CPU rising edge

(with the skew making CPU early).

PD#

This is an asynchronous active low input pin used to power

down the device into a low power state. The internal clocks

are disabled and the VCO and Crystal are stopped. Power

down will also place all the outputs in a low state at the end of

their current cycle. The latency of power down will not be

greater than 3ms.

CPU_STOP#

This is a synchronous active low input pin used to stop the

CPUCLK clocks in an active low state. All other clocks will

continue to run while this function is enabled. The CPUCLKs

will have a turn ON latency of at least 3 CPU clocks.

PCI_STOP#

This is a synchronous active low input pin used to stop the

PCICLK clocks in an active low state. It will not effect

PCICLK_F nor any other outputs.