Integrated

Circuit

Systems, Inc.

ICS9248-98

Third party brands and names are the property of their respective owners.

Block Diagram

9248-98 Rev D 11/6/00

Functionality

Pin Configuration

48-Pin 300mil SSOP

Recommended Application:

440BX/VIA Apollo 133 style chipset.

Output Features:

•

2 - CPUs @2.5V, up to 166MHz.

•

1 - IOAPIC @ 2.5V

•

13 - SDRAM @ 3.3V

•

6 - PCI @3.3V,

•

1 - 48MHz, @3.3V fixed.

•

1 - 24MHz @ 3.3V

•

2 - REF @3.3V, 14.318MHz.

Features:

•

Up to 166MHz frequency support

•

Support power management: PCI, CPU stop and Mode

•

Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).

•

Uses external 14.318MHz crystal

Skew Specifications:

•

CPU – CPU: <175ps

•

SDRAM - SDRAM: <250ps

•

PCI – PCI: <500ps

•

BUFFER_IN-SDRAM: <5ns

•

CPU(early)-PCI: Min=1.0ns, Typ=2.3ns, Max=4.0ns

Frequency Generator & Integrated Buffers for Celeron & PII/III™

CLK_STOP#

PCI_STOP#

PLL2

PLL1

Spread

Spectrum

48MHz

24MHz

IOAPIC

CPUCLK_F

CPUCLK 1

SDRAM (11:0)

PCICLK (4:0)

PCICLKF

SDRAM_F

X1

X2

BUFFER IN

XTAL

OSC

PCI

CLOCK

DIVDER

STOP

STOP

STOP

STOP

SDATA

SCLK

FS(3:0)

MODE

Control

Logic

Config.

Reg.

/2

REF(1:0)

LATCH

POR

2

12

5

4

4

* Internal Pull-up Resistor of 120K to VDD

** Internal Pull-down resistor of 120K to GND

3

S

F2

S

F1

S

F0

S

F

U

P

C

)

z

H

M

(

K

L

C

I

C

P

)

z

H

M

(

0000

0

0

.

0

80

0

.

0

4

000

1

0

0

.

5

70

5

.

7

3

00

1

0

1

3

.

3

85

6

.

1

4

00

11

2

8

.

6

61

4

.

3

3

01

0

0

0

0

.

3

0

13

3

.

4

3

01

01

1

0

.

2

1

14

3

.

7

3

01

1

0

1

0

.

8

61

0

.

4

3

0

111

3

2

.

0

0

11

4

.

3

3

1

000

0

0

.

0

2

10

0

.

0

4

10

0

1

9

9

.

4

1

13

3

.

8

3

10

10

9

9

.

9

0

16

6

.

6

3

10

1

1

0

0

.

5

0

10

0

.

5

3

11

00

0

0

.

0

4

10

0

.

5

3

11

0

1

0

0

.

0

5

10

5

.

7

3

111

0

0

0

.

4

2

10

0

.

1

3

1111

9

9

.

2

3

15

2

.

3

3

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

information being relied upon by the customer is current and accurate.

VDD1

*PCI_STOP/REF0

GND

X1

X2

VDD2

*MODE/PCICLK_F

**FS3/PCICLK0

GND

PCICLK1

PCICLK2

PCICLK3

PCICLK4

VDD2

BUFFER IN

GND

SDRAM11

SDRAM10

VDD3

SDRAM9

SDRAM8

GND

SDATA

SCLK

VDDL1

IOAPIC

REF1/FS2*

GND

CPUCLK_F

CPUCLK1

VDDL2

CLK_STOP#*

SDRAM_F

GND

SDRAM0

SDRAM1

VDD3

SDRAM2

SDRAM3

GND

SDRAM4

SDRAM5

VDD3

SDRAM6

SDRAM7

VDD4

48MHz/FS0*

24MHz/FS1*

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25