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IDT72V01 Datasheet(PDF) 6 Page - Integrated Device Technology

Part # IDT72V01
Description  3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9
PDF  13 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72V01 Datasheet(HTML) 6 Page - Integrated Device Technology

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5.08
6
IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9
COMMERCIAL TEMPERATURE RANGE
low after 512/1024/2048/4096 writes to the IDT72V01/72V02/
72V03/72V04.
EMPTY FLAG (
EF
EF)
The Empty Flag (
EF) will go low, inhibiting further read
operations, when the read pointer is equal to the write pointer,
indicating that the device is empty.
EXPANSION OUT/HALF-FULL FLAG (
XO
XO/HF
HF)
This is a dual-purpose output. In the single device mode,
when Expansion In (
XI) is grounded, this output acts as an
indication of a half-full memory.
After half of the memory is filled and at the falling edge of
the next write operation, the Half-Full Flag (
HF) will be set low
and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (
HF) is then
reset by using rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (
XI) is con-
nected to Expansion Out (
XO) of the previous device. This
output acts as a signal to the next device in the Daisy Chain
by providing a pulse to the next device when the previous
device reaches the last location of memory.
Figure 2. Reset
NOTES:
1.
EF, FF, HF may change status during Reset, but flags will be valid at tRSC.
2.
W and R = VIH around the rising edge of RS.
Figure 3. Asynchronous Write and Read Operation
HFH
t RSC
t RS
t RSS
t RSS
t EFL
, t FFH
t
RS
W
R
EF
HF, FF
t RSR
2679 drw 04
t A
R
t RC
DATA OUT VALID
DATA OUT VALID
t RPW
t RLZ
t DV
t A
t RHZ
t RR
t WC
t WR
t WPW
DATA IN VALID
DATA IN VALID
tDS
tDH
Q0 – Q8
2679 drw 05
W
D0 – D8



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