28F320J5 datasheet(48/53 Pages) INTEL

48 / 53 page

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

ADVANCE INFORMATION

6.6

AC Characteristics— Write Operations(1,2)

Versions

Valid for All

Speeds

Sym

Parameter

Notes

Min

Max

Unit

tPHWL (tPHEL)

RP# High Recovery to WE# (CE

X ) Going

Low

µs

tELWL (tWLEL)CE

X (WE#) Low to WE# (CEX) Going Low

tWP

Write Pulse Width

tDVWH (tDVEH)

Data Setup to WE# (CE

X ) Going High

tAVWH (tAVEH)

Address Setup to WE# (CE

X ) Going High

tWHEH (tEHWH)

X (WE#) Hold from WE# (CEX) High

tWHDX (tEHDX)

Data Hold from WE# (CE

X ) High

tWHAX (tEHAX)

Address Hold from WE# (CE

X ) High

tWPH

Write Pulse Width High

W10

tPHHWH (tPHHEH)

RP# VHH Setup to WE# (CE

X ) Going High

W11

tVPWH (tVPEH)

VPEN Setup to WE# (CE

X ) Going High

W12

tWHGL (tEHGL)

Write Recovery before Read

W13

tWHRL (tEHRL)

WE# (CE

X ) High to STS Going Low

W14

tQVPH

RP# VHH Hold from Valid SRD, STS Going

High

3,5,7

W15

tQVVL

VPEN Hold from Valid SRD, STS Going High

3,5,7

NOTES:

CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0,

CE1, or CE2 that disables the device (see Table 2, Chip Enable Truth Table).

Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during

read-only operations. Refer to

AC Characteristics–Read-Only Operations.

A write operation can be initiated and terminated with either CEX or WE#.

Sampled, not 100% tested.

Refer to Table 4 for valid AIN and DIN for block erase, program, or lock-bit configuration.

STS timings are based on STS configured in its RY/BY# default mode.

For array access, tAVQV is required in addition to tWHGL for any accesses after a write.

VPEN should be held at VPENH (and if necessary RP# should be held at VHH) until determination of block erase, program, or

lock-bit configuration success (SR.1/3/4/5 = 0).

Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low first) to CEX or WE# going high

(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. If CEX is driven low 10 ns before WE# going low,

WE# pulse width requirement decreases to tWP - 10 ns.

Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going low

(whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.

28F320J5 Datasheet(PDF) 48 Page - Intel Corporation

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