S80296 datasheet(29/40 Pages) INTEL

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PRELIMINARY

80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

WHBX

BHE#, INST Hold after WR# Rising Edge

WHAX

A19:0, CS

x# Hold after WR# Rising Edge

RHBX

BHE#, INST Hold after RD# Rising Edge

RHAX

A19:0, CS

x# Hold after RD# Rising Edge

Table 11. AC Characteristics the External Memory System Must Meet, Demultiplexed Bus Mode

Symbol

Parameter

Min

Max

Units

AVDV

A19:0 Valid to Input Data Valid

4t – 28

ns (1, 2, 3)

RLDV

RD# Active to Input Data Valid

3t – 25

ns (1, 2)

SLDV

Chip Select Low to Data Valid

4t – 28

ns (1, 2, 3)

CHDV

CLKOUT High to Input Data Valid

2t – 25

RHDZ

End of RD# to Input Data Float

ns (2, 3)

RXDX

Data Hold after RD# Inactive

AVYV

A19:0 Valid to READY Setup

3t – 45

ns (4)

1YX

First READY Hold (active) after CLKOUT High

t – 4

2t – 21

ns (5, 6)

2YX

Non-first READY Hold (active) after CLKOUT High

2t – 21

ns (5)

YLYH

Non READY (inactive) Time

No Upper

Limit

NOTES:

If using the READY signal to insert wait states, you must program at least one wait state in the

BUSCON

x register because the first falling edge of READY is not synchronized with a CLKOUT edge.

If using the BUSCON

x register without the READY signal to insert wait states, add 2t

× n, where n =

number of wait states.

If CS

x# changes or if a write cycle follows a read cycle, add 2t (1 state).

If using the BUSCON

x register to insert wait states, add (2t

× n–1), where n = number of wait states.

Exceeding the maximum specification causes additional wait states.

If you program two or more wait states in the BUSCON

x register, the T

1YX minimum does not apply.

Table 10. AC Characteristics the 80C296SA Will Meet, Demultiplexed Bus Mode (Continued)

Symbol

Parameter

Min

Max

Units

NOTES:

25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz

can be applied with an external clock source.

When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8

MHz. The PLL cannot be run at frequencies lower than 16 MHz.

If using either READY or BUSCON

x to insert wait states, add 2t

× n, where n = number of wait states.

Assuming back-to-back bus cycles.

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