80C188EB13 datasheet(59/59 Pages) INTEL

59 / 59 page

80C186EB80C188EB 80L186EB80L188EB

ERRATA

An 80C186EB80L186EB with a STEPID value of

0001H has the following known errata A device with

a STEPID of 0001H can be visually identified by the

presence

of an ‘‘A’’ alpha character next to the

FPO number The FPO number location is shown in

Figures 4 5 and 6

1 A19ONCE is not latched by the rising edge of

RESIN A19ONCE must remain active (LOW) at

all times to remain in the ONCE Mode Removing

A19ONCE after RESIN is high will return all out-

put pins to a driving state

however

the

80C186EB will remain in a reset state

2 During interrupt acknowledge (INTA) bus cycles

the bus controller will ignore the state of the

READY pin if the previous bus cycle ignored the

state of the READY pin This errata can only oc-

cur if the Chip-Select Unit is being used All active

chip-selects must be programmed to use READY

(RDY bit must be programmed to a 1) if wait-

states are required for INTA bus cycles

3 CLKOUT will transition off the rising edge of

CLKIN rather than the falling edge of CLKIN This

does not affect any bus timings other than TCD

4 RESIN has a hysterisis of only 130 mV It is rec-

ommended that RESIN be driven by a Schmitt

triggered device to avoid processor lockup during

reset using an RC circuit

5 SINT1 will only go active for one clock period

when a receive or transmit interrupt is pending

(ie

it does not remain active until the S1STS

any of the processor interrupt lines (INT0 – INT4)

then it must be latched by user logic

An 80C186EB80L186EB with a STEPID value of

0001H or 0002H has the following known errata A

device with a STEPID of 0002H can be visually iden-

tified by noting the presence of a ‘‘B’’ ‘‘C’’ ‘‘D’’ or

‘‘E’’ alpha character next to the FPO number The

FPO number location is shown in Figures 4 5 and 6

1 An internal condition with the interrupt controller

can cause no acknowledge cycle on the INTA1

line in response to INT1 This errata only occurs

when Interrupt 1 is configured in cascade mode

and a higher priority interrupt exists This errata

will not occur consistantly it is dependent on in-

terrupt timing

REVISION HISTORY

This data sheet replaces the following data sheets

270803-004 80C186EB

270885-003 80C188EB

270921-003 80L186EB

270920-003 80L188EB

272311-001 SB80C188EBSB80L188EB

272312-001 SB80C186EBSB80L186EB

80C188EB13 Datasheet(PDF) 59 Page - Intel Corporation

80C188EB13 Datasheet(HTML) 59 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL