87C51F datasheet(14/18 Pages) INTEL

14 / 18 page

AUTOMOTIVE 87C51FAFBFCFC-20

AC TESTING INPUT OUTPUT WAVEFORMS

270961 – 17

AC Inputs during testing are driven at VCCb05V for a Logic ‘‘1’’

and 045V for a Logic ‘‘0’’ Timing measurements are made at VIH

min for a Logic ‘‘1’’ and VIL max for a Logic ‘‘0’’

FLOAT WAVEFORMS

270961 – 18

For timing purposes a port pin is no longer floating when a

100 mV change from load voltage occurs and begins to float

when a 100 mV change from the loaded VOH VOL level occurs

IOL IOH t g20 mA

Table 3 EPROM Programming Modes

Mode

RST

PSEN

ALE

P26

P27

P33

P36

P37

PROG

VPP

Program Code Data

1275V

Verify Code Data

Program Encryption

1275V

Array Address 0 – 3FH

Program Lock

Bit 1

1275V

Bits

Bit 2

1275V

Bit 3

1275V

Read Signature Byte

DEFINITION OF TERMS

(EPROM PROGRAMMING)

ADDRESS LINES

P10 – P17 P20 – P25 P34 –

P35 respectively for A0 – A13

DATA LINES

P00 – P07 for D0 – D7

CONTROL SIGNALS

RST PSEN P26 P27 P33

P36 P37

PROGRAM SIGNALS

ALEPROG EA VPP

PROGRAMMING THE EPROM

The part must be running with a 4 MHz to 6 MHz

oscillator The address of an EPROM location to be

programmed is applied to address lines while the

code byte to be programmed in that location is ap-

plied to data lines Control and program signals must

be held at the levels indicated in Table 3 Normally

EA VPP is held at logic high until just before ALE

PROG is to be pulsed The EA VPP is raised to VPP

ALEPROG is pulsed low and then EA VPP is re-

turned to a high (also refer to timing diagrams)

NOTE

Exceeding the VPP maximum for any amount of

time could damage the device permanently The

VPP source must be well regulated and free of

glitches

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