INDEX61075MHZ datasheet(13/48 Pages) INTEL

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PENTIUM

PROCESSOR (610\75)

1/16/97 9:25 AM

24232302.DOC

INTEL CONFIDENTIAL

(until publication date)

Table 3. Quick Pin Reference (Contd.)

Symbol

Type

Name and Function

[BF]

Bus Frequency determines the bus -to-core frequency ratio. BF is sampled at

RESET, and cannot be changed until another non-warm ( 1 ms) assertion of

RESET. Additionally, BF must not change values while RESET is active.

For

proper operation of the Pentium processor (610\75) this pin should be strapped

high or low. When BF is strapped to V cc, the processor will operate at a 2/3

bus/core frequency ratio. When BF is strapped to V ss, the processor will

operate at a 1/2 bus/core frequency ratio. If BF is left floating, the Pentium

processor (610\75) defaults to a 2/3 bus ratio. Note the Pentium processor

(610\75) will not operate at a 1/2 bus/core frequency ratio.

BOFF#

The backoff input is used to abort all outstanding bus cycles that have not yet

completed. In response to BOFF#, the Pentium processor (610\75) will float all

pins normally floated during bus hold in the next clock. The processor remains

in bus hold until BOFF# is negated, at which time the Pentium processor

(610\75) restarts the aborted bus cycle(s) in their entirety.

BP[3:2]

PM/BP[1:0]

The breakpoint pins (BP3-0) correspond to the debug registers, DR3-DR0.

These pins externally indicate a breakpoint match when the debug registers are

programmed to test for breakpoint matches.

BP1 and BP0 are multiplexed with the performance monitoring pins (PM1

and PM0). The PB1 and PB0 bits in the Debug Mode Control Register

determine if the pins are configured as breakpoint or performance monitoring

pins. The pins come out of RESET configured for performance monitoring.

BRDY#

The burst ready input indicates that the external system has presented valid

data on the data pins in response to a read or that the external system has

accepted the Pentium processor (610\75) data in response to a write request.

This signal is sampled in the T2, T12 and T2P bus states.

BREQ

The bus request output indicates to the external system that the Pentium

processor (610\75) has internally generated a bus request. This signal is

always driven whether or not the Pentium processor (610\75) is driving its bus.

BUSCHK#

The bus check input allows the system to signal an unsuccessful completion

of a bus cycle. If this pin is sampled active, the Pentium processor (610\75) will

latch the address and control signals in the machine check registers. If, in

addition, the MCE bit in CR4 is set, the Pentium processor (610\75) will vector

to the machine check exception.

CACHE#

For Pentium processor (610\75) -initiated cycles the cache pin indicates internal

cacheability of the cycle (if a read), and indicates a burst writeback cycle (if a

write). If this pin is driven inactive during a read cycle, the Pentium processor

(610\75) will not cache the returned data, regardless of the state of the KEN#

pin. This pin is also used to determine the cycle length (number of transfers in

the cycle).

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