M80C287 datasheet(13/29 Pages) INTEL

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M80C287

Table 9 CERDIP Pin Cross-Reference

CERDIP

Name

Package

CLK

CKM

RESET

PEREQ

PEACK

BUSY

ERROR

D10

D11

D12

D13

D14

D15

NPRD

NPWR

NPS1

NPS2

CMD0

CMD1

VCC

39133740

VSS

14103038

No Connect

CLOCK (CLK)

This input provides the basic timing for internal oper-

ation This pin does not require MOS-level input it

will operate at either TTL or MOS levels up to the

maximum allowed frequency A minimum frequency

must be provided to keep the internal logic properly

functioning Depending on the signal on CKM the

signal on CLK can be divided by two to produce the

internal clock signal

CLOCKING MODE (CKM)

This pin is a strapping option When it is strapped to

VCC (HIGH) the CLK input is used directly when

strapped to VSS (LOW) the CLK input is divided by

two to produce the internal clock signal During the

RESET sequence this input must be stable at least

four internal clock cycles (ie CLK clocks when CKM

is HIGH 2 c CLK clocks when CKM is LOW) before

RESET goes LOW

SYSTEM RESET (RESET)

A LOW to HIGH transition on this pin causes the

M80C287 to terminate its present activity and to en-

ter a dormant state RESET must remain active

(HIGH) for at least four CLK periods (ie the RESET

signal presented to the M80C287 must be at least

four M80C287 clocks long regardless of the fre-

quency of the CPU) Note that the M80C287 is ac-

tive internally for 25 clock cycles after the termina-

tion of the RESET signal (the HIGH to LOW tran-

sition of RESET)

therefore

the first instruction

should not be written to the M80C287 until 25 clocks

after the falling edge of RESET Table 10 shows the

status of the output pins during the reset sequence

After a reset all output pins return to their inactive

states

Table 10 Output Pin Status during Reset

Output Pin Name

Value During Reset

BUSY

HIGH

ERROR

HIGH

PEREQ

LOW

D15–D0

Tristate OFF

PROCESSOR EXTENSION REQUEST (PEREQ)

When active this pin signals to the CPU that the

M80C287 is ready for data transfer tofrom its data

FIFO With M80286 or M80C286 CPUs PEREQ can

be deactivated after assertion of PEACK These

CPUs rely on the NPX to deassert PEREQ when all

operands have been transfered When there are

more than five data transfers PEREQ is deactiviated

after the first three transfers and subsequently after

every four transfers This signal always goes inactive

before BUSY goes inactive

BUSY STATUS (BUSY)

When active this pin signals to the CPU that the

M80C287 is currently executing an instruction It

should be connected to the CPU’s BUSY pin During

the RESET sequence this pin is HIGH

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