CS80C88 datasheet(14/32 Pages) INTERSIL

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3-14

The 80C88 and 80C86 are completely software compatible

by virtue of their identical execution units. Software that is

system dependent may not be completely transferable, but

software that is not system dependent will operate equally

as well on an 80C88 or an 80C86.

The hardware interface of the 80C88 contains the major

differences between the two CPUs. The pin assignments are

nearly identical, however, with the following functional

changes:

• A8-A15: These pins are only address outputs on the

80C88. These address lines are latched internally and

remain valid throughout a bus cycle in a manner similar to

the 8085 upper address lines.

• BHE has no meaning on the 80C88 and has been elimi-

nated.

• SS0 provides the S0 status information in the minimum

mode. This output occurs on pin 34 in minimum mode

only. DT/R, IO/M and SS0 provide the complete bus status

in minimum mode.

• IO/M has been inverted to be compatible with the 8085

bus structure.

• ALE is delayed by one clock cycle in the minimum mode

when entering HALT, to allow the status to be latched with

ALE.

A7-A0

DATA IN

CLK

QS1, QS0

S2, S1, S0

A19/S6 - A16/S3

ALE

80C88

AD7 - AD0

DEN

S6 - S3

DT/R

MRDC

82C84

RDY

READY

80C88

A19 - A16

A15 - A8

FIGURE 21. MEDIUM COMPLEXITY SYSTEM TIMING

A15 - A8

80C88

DATA OUT

80C88

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