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CS80C88 Datasheet(PDF) 25 Page - Intersil Corporation |
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CS80C88 Datasheet(HTML) 25 Page - Intersil Corporation |
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25 / 32 page ![]() 3-25 AC Test Circuit AC Testing Input, Output Waveform FIGURE 30. RESET TIMING Waveforms (Continued) VCC CLK RESET ≥ 50µs ≥ 4 CLK CYCLES (7) TCLDX1 (6) TDVCL OUTPUT FROM DEVICE UNDER TEST TEST CL (NOTE) POINT NOTE: Includes stay and jig capacitance. INPUT VIH + 20% VIH VIL - 50% VIL OUTPUT VOH VOL 1.5V 1.5V AC Testing: All input signals (other than CLK) must switch between VILMAX -50% VIL and VIHMIN +20% VIH. CLK must switch between 0.4V and VCC -0.4V. Input rise and fall times are driven at 1ns/V. Burn-In Circuits MD80C88 (CERDIP) 33 34 35 36 37 38 40 32 31 30 29 24 25 26 27 28 21 22 23 13 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 39 GND GND NMI INTR CLK GND 1 RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RC RI RI VCC/2 VCL VCL VIL GND VCC/2 VCC/2 RI VCC/2 VCC/2 VCC/2 VCL VCC GND RIO RO RO RO VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 GND VCL NODE FROM PROGRAM CARD GND GND VCL GND GND VCL GND GND GND VCL VCL VCL OPEN OPEN OPEN OPEN GND GND F0 RO RO RO RO RO RO RO RO RO RO A A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VCC QS2 TEST READY RESET A15 A16 A17 A18 A19 BHE MX RD RQ0 RQ1 LOCK S2 S1 S0 QS0 C 80C88 |
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