4-19

Doubled Sampling Speed

The phase control and both positive and negative true chip

enables allow the parallel connection of two CA3306s to

double the sampling speed. Figure 18 shows this configura-

tion. One converter samples on the positive phase of the

clock, and the second on the negative. The outputs are also

alternately enabled. Care should be taken to provide a near

square-wave clock it operating at close to the maximum

clock speed for the devices.

8-Bit to 12-Bit Conversion Techniques

To obtain 8-bit to 12-bit resolution and accuracy, use a feed-

forward conversion technique. Two A/D converters will be

needed to convert up to 11 bits; three A/D converters to con-

vert 12 bits. The high speed of the CA3306 allows 12-bit

conversions in the 500ns to 900ns range.

The circuit diagram of a high-speed 12-bit A/D converter is

shown in Figure 19. In the feed-forward conversion method

two sequential conversions are made. Converter A first does

a coarse conversion to 6 bits. The output is applied to a 6-bit

D/A converter whose accuracy level is good to 12 bits. The

D/A converter output is then subtracted from the input volt-

age, multiplied by 32, and then converted by a second flash

A/D converter, which is connected in a 7-bit configuration.

The answers from the first and second conversions are

added together with bit 1 of the first conversion overlapping

bit 7 of the second conversion.

When using this method, take care that:

• An offset bias of 1 LSB (1/64) Is subtracted from the first

conversion since the second converter is unipolar.

• The D/A converter and its reference are accurate to the

total number of bits desired for the final conversion (the A/D

converter need only be accurate to 6 bits).

The first converter can be offset-biased by adding a 20

Ω

resistor at the bottom of the ladder and increasing the refer-

ence voltage by 1 LSB. If a 6.4V reference is used in the sys-

tem, for example, then the first CA3306 will require a 6.5V

reference.

Definitions

Dynamic Performance Definitions

Fast Fourier Transform (FFT) techniques are used to evaluate

the dynamic performance of the converter. A low distortion

sine wave is applied to the input, it is sampled, and the output

is stored in RAM. The data is then transformed into the

frequency domain with a 4096 point FFT and analyzed to

evaluate the dynamic performance of the A/D. The sine wave

input to the part is -0.5dB down from full scale for all these

tests.

Signal-to-Noise (SNR)

SNR is the measured RMS signal to RMS noise at a

specified input and sampling frequency. The noise is the

RMS sum of all of the spectral components except the

fundamental and the first five harmonics.

Signal-to-Noise + Distortion Ratio (SINAD)

SINAD is the measured RMS signal to RMS sum of all other

spectral components below the Nyquist frequency excluding DC.

Effective Number of Bits (ENOB)

The effective number of bits (ENOB) is derived from the

SINAD data. ENOB is calculated from:

where:

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the first 5 harmonic

components to the RMS value of the measured input signal.

Operating and Handling Considerations

HANDLING

All inputs and outputs of Intersil CMOS devices have a

network for electrostatic protection during handling. Recom-

mended handling practices for CMOS devices are described

in AN6525. “Guide to Better Handling and Operation of

CMOS Integrated Circuits.”

OPERATING

Operating Voltage

During operation near the maximum supply voltage limit,

care should be taken to avoid or suppress power supply

turn-on and turn-off transients, power supply ripple, or

ground noise; any of these conditions must not cause

Input Signals

To prevent damage to the input protection circuit, input

Input currents must not exceed 20mA even when the power

supply is off. The zener (pin 4) is the only terminal allowed to

Unused Inputs

A connection must be provided at every input terminal. All

Output Short Circuits

devices by exceeding the maximum device dissipation.

CA3306, CA3306A, CA3306C