7-640

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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CD14538BMS

CMOS Dual Precision

Monostable Multivibrator

Description

CD14538BMS dual precision monostable multivibrator provides stable retrigger-

able/resettable one-shot operation for any fixed-voltage timing application.

put pulse widths from the Q and Q terminals. The time delay from trigger input to

output transition (trigger propagation delay) and the time delay from reset input

cision control of output pulse widths is achieved through linear CMOS tech-

niques.

Leading-edge-triggering (+TR) and trailing-edge-triggering (-TR) inputs are pro-

vided for triggering from either edge of an input pulse. An unused +TR input

should be tied to VSS. An unused -TR input should be tied to VDD. A RESET

(on low level) is provided for immediate termination of the output pulse or to pre-

vent output pulses when power is turned on. An unused RESET input should be

tied to VDD. However, if an entire section of the CD14538BMS is not used, its

inputs must be tied to either VDD or VSS. See Table 1.

In normal operation the circuit retriggers (extends the output pulse one period)

on the application of each new trigger pulse. For operation in the non-retrigger-

able mode, Q is connected to -TR when leading-edge triggering (+TR) is used

or Q is connected to +TR when trailing-edge triggering (-TR) is used. The time

The CD14538BMS is interchangeable with type MC14538 and is similar to and

pin-compatible with the CD4098B* and CD4538B**.

The CD14538BMS is supplied in these 16-lead outline packages:

Braze Seal DIP

H4X

Frit Seal DIP

H1L

Ceramic Flatpack H6W

Features

• High-Voltage Type (20V Rating)

• Retriggerable/Resettable Capability

• Trigger and Reset Propagation Delays Inde-

pendent of RX, CX

• Triggering From Leading or Trailing Edge

• Q and Q Buffered Outputs Available

• Separate Resets

• Wide Range of Output-Pulse Widths

• Schmitt-Trigger Input Allows Unlimited Rise

and Fall Times On +TR and -TR Inputs

• 100% Tested For Maximum Quiescent Cur-

rent at 20V

• Maximum Input Current of 1

µA at 18V Over

Full Package-Temperature Range:

• Noise Margin (Full Package-Temperature

Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• 5V, 10V and 15V Parametric Ratings

• Standardized Symmetrical Output Charac-

teristics

• Meets All Requirements of JEDEC Tentative

Standards No. 13B, “Standard Specifica-

tions for Description of “B” Series CMOS

Device’s

Applications

• Pulse Delay and Timing

• Pulse Shaping

November 1994

File Number

3192

Pinout

CD14538BMS

TOP VIEW

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

RESET (1)

+TR (1)

-TR (1)

Q1

Q1

RESET (2)

+TR (2)

-TR (2)

Q2

Q2

Functional Diagram

CX1

RX1

VDD

2

1

RXCX(1)

6

7

10

9

4

5

3

12

11

13

15

14 RXCX(2)

VDD

CX2

RX2

Q1

Q1

Q2

Q2

+TR

-TR

RESET

+TR

-TR

RESET

VDD = 16

VSS = 8