AD7794/AD7795

Rev. D | Page 15 of 36

CHOP DISABLED

With chop disabled, the switching time or settling time is

reduced by a factor of two. However, periodic offset calibrations

may now be required to remove offset and offset drift. When

chop is disabled, the AMP-CM bit in the mode register should

be set to 1. This limits the allowable common-mode voltage that

can be used. However, the common-mode rejection degrades if

the bit is not set.

Table 11 shows the rms noise of the AD7794/AD7795 for some

of the update rates and gain settings with chop disabled.

The numbers given are for the bipolar input range with the

internal 1.17 V reference. These numbers are typical and are

generated with a differential input voltage of 0 V.

Table 12 and Table 13 show the effective resolution while the

output peak-to-peak (p-p) resolution is listed in brackets. It is

important to note that the effective resolution is calculated

using the rms noise, while the p-p resolution is calculated based

on peak-to-peak noise. The p-p resolution represents the

resolution for which there is no code flicker. These numbers are

typical and rounded to the nearest LSB.

Table 11. RMS Noise (μV) vs. Gain and Output Update Rate Using an Internal 1.17 V Reference with Chop Disabled

Update Rate (Hz)

Gain of 1

Gain of 2

Gain of 4

Gain of 8

Gain of 16

Gain of 32

Gain of 64

Gain of 128

4.17

1.22

0.98

0.33

0.18

0.13

0.062

0.053

0.051

8.33

1.74

1.53

0.49

0.29

0.21

0.1

0.079

0.07

16.7

2.64

2.44

0.79

0.48

0.33

0.16

0.13

0.12

33.2

4.55

3.52

1.11

0.66

0.46

0.21

0.17

0.16

62

5.03

4.45

1.47

0.81

0.58

0.27

0.2

0.22

123

8.13

7.24

2.27

1.33

0.96

0.48

0.36

0.37

242

15.12

13.18

3.77

2.09

1.45

0.64

0.5

0.47

470

17.18

14.63

8.86

2.96

1.92

0.89

0.69

0.7

Table 12.

Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7794 Using an Internal 1.17 V Reference with Chop Disabled

Update Rate (Hz)

Gain of 1

Gain of 2

Gain of 4

Gain of 8

Gain of 16

Gain of 32

Gain of 64

Gain of 128

4.17

21 (18.5)

20 (17.5)

21 (18.5)

20.5 (18)

20 (17.5)

20 (17.5)

19.5 (17)

18.5 (16)

8.33

20.5 (18)

19.5 (17)

20 (17.5)

20 (17.5)

19.5 (17)

19.5 (17)

19 (16.5)

18 (15.5)

16.7

20 (17.5)

19 (16.5)

19.5 (17)

19 (16.5)

19 (16.5)

19 (16.5)

18 (15.5)

17 (14.5)

33.2

19 (16.5)

18.5 (16)

19 (16.5)

19 (16.5)

18.5 (16)

18.5 (16)

17.5 (15)

17 (14.5)

62

19 (16.5)

18 (15.5)

18.5 (16)

18.5 (16)

18 (15.5)

18 (15.5)

17.5 (15)

16.5 (14)

123

18 (15.5)

17.5 (15)

18 (15.5)

17.5 (15)

17 (14.5)

17 (14.5)

16.5 (14)

15.5 (13)

242

17 (14.5)

16.5 (14)

17 (14.5)

17 (14.5)

16.5 (14)

17 (14.5)

16 (13.5)

15 (12.5)

470

17 (14.5)

16.5 (14)

16 (13.5)

16.5 (14)

16 (13.5)

16.5 (14)

15.5 (13)

14.5 (12)

Table 13.

Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7795 Using an Internal 1.17 V Reference with Chop Disabled

Update Rate (Hz)

Gain of 1

Gain of 2

Gain of 4

Gain of 8

Gain of 16

Gain of 32

Gain of 64

Gain of 128

4.17

16 (16)

16 (16)

16 (16)

16 (16)

16 (16)

16 (16)

16 (16)

16 (16)

8.33

16 (16)

16 (16)

16 (16)

16 (16)

16 (16)

16 (16)

16 (16)

16 (15.5)

16.7

16 (16)

16 (16)

16 (16)

16 (16)

16 (16)

16 (16)

16 (15.5)

16 (14.5)

33.2

16 (16)

16 (16)

16 (16)

16 (16)

16 (16)

16 (16)

16 (15)

16 (14.5)

62

16 (16)

16 (15.5)

16 (16)

16 (16)

16 (15.5)

16 (15.5)

16 (15)

16 (14)

123

16 (15.5)

16 (15)

16 (15.5)

16 (15)

16 (14.5)

16 (14.5)

16 (14)

15.5 (13)

242

16 (14.5)

16 (14)

16 (14.5)

16 (14.5)

16 (14)

16 (14.5)

16 (13.5)

15 (12.5)

470

16 (14.5)

16 (14)

16 (13.5)

16 (14)

16 (13.5)

16 (14)

15.5 (13)

14.5 (12)