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CD4012BMS Datasheet(PDF) 7 Page - Intersil Corporation |
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CD4012BMS Datasheet(HTML) 7 Page - Intersil Corporation |
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7 / 9 page  7-59 CD4011BMS, CD4012BMS, CD4023BMS Schematic and Logic Diagrams CD4011BMS CD4023BMS CD4012BMS 1 * 2 * (8, 6, 13) p n (9, 5, 12) n p VDD 14 1(8, 6,13) 2(9, 5, 12) 3 (10, 4, 11) LOGIC DIAGRAM p p p n n n 7 VSS 3 (10, 4, 11) VDD VSS *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK 1 OF 4 GATES (NUMBERS IN PARENTHESES ARE TERMINAL NUMBERS FOR OTHER GATES) VDD VSS 3(1, 11) 5(8, 13) 6 (9, 10) LOGIC DIAGRAM VSS 7 4(2, 12) 5 *(8, 13) 4 *(2, 12) 3 *(1, 11) p n 6(9, 10) n n n n n n p p p p p p VDD 14 *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK 1 OF 3 GATES (NUMBERS IN PARENTHESES ARE TERMINAL NUMBERS FOR OTHER GATES) VDD VSS 2(12) 4(10) 1 (13) 5(9) 3(11) LOGIC DIAGRAM p p p p p p p p p n n n n n n n n n 7 VSS 1 (13) 14 VDD 2 *(12) 3 *(11) 4 *(10) 5 *(9) 1 OF 2 GATES (NUMBERS IN PARENTHESES ARE TERMINAL NUMBERS FOR OTHER GATES) *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK |
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